Logic Gates

8-Bit Bitwise XNOR Gate

An 8-bit combinational logic gate that performs bitwise XNOR operations on two input vectors.

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About this block

Simulate it in the Verilog IDE

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8-Bit Bitwise XNOR Gate is a Verilog reference block in the Logic Gates catalog. AND, OR, XOR, and other combinational gate and boolean logic primitives. Marked Easy: a small block you can read, simulate, and synthesize in one sitting.

This IP implements an 8-bit bitwise XNOR (exclusive-NOR) logic gate. It performs a bitwise comparison of two 8-bit input vectors. The output bit is high when the corresponding input bits are equal, and low when they differ. The design is purely combinational, ensuring minimal logic depth and no clock dependencies. It is suitable for parity checking, equality comparison, and data masking tasks.

Choose Open in IDE. RTL Studio loads the packaged workspace for 8-Bit Bitwise XNOR Gate.
Read the Verilog module in the editor. The catalog line for this block: An 8-bit combinational logic gate that performs bitwise XNOR operations on two input vectors.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Architecture

The design computes the XOR of inputs a and b, then inverts the result to produce the XNOR output. This is a purely combinational logic block with no clock dependencies.

Ports

Port	Direction	Width	Description
a	Input	[7:0]	First 8-bit operand
b	Input	[7:0]	Second 8-bit operand
y	Output	[7:0]	Result of bitwise XNOR

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