Logic Gates

2-Input NOR Gate

A simple 2-input NOR gate module for combinational logic.

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About this block

Simulate it in the Verilog IDE

Easyverilogsimsyn

2-Input NOR Gate is a Verilog reference block in the Logic Gates catalog. AND, OR, XOR, and other combinational gate and boolean logic primitives. Marked Easy: a small block you can read, simulate, and synthesize in one sitting.

This OpenIP provides a synthesizable, 2-input NOR gate implemented in Verilog.

It is designed for educational purposes, basic logic synthesis, and integration into larger digital systems.

The module is lightweight, combinational, and supports standard CMOS processes.

Choose Open in IDE. RTL Studio loads the packaged workspace for 2-Input NOR Gate.
Read the Verilog module in the editor. The catalog line for this block: A simple 2-input NOR gate module for combinational logic.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Architecture

The design consists of a single combinational logic cell. Input signals a and b are combined using the NOR operator. The output out is driven immediately based on input states.

Ports

Port	Direction	Width	Description
a	Input	1	First input
b	Input	1	Second input
out	Output	1	NOR result

Verification

The testbench (tb/tb_nor_gate_2input.v) verifies all four input combinations against the standard NOR truth table.

Test Case	a	b	Expected out	Result
TC1	0	0	1	PASS
TC2	0	1	0	PASS
TC3	1	0	0	PASS
TC4	1	1	0	PASS

All tests passed successfully in the simulation run. The simulation log confirms correct logical behavior.

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