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Logic Gates

XOR-Reduce Tree 8-bit

An 8-bit XOR-reduce tree that computes the parity of an 8-bit input vector using a hierarchical binary tree structure.

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About this block

Simulate it in the Verilog IDE

Easyverilogsimsyn

XOR-Reduce Tree 8-bit is a Verilog reference block in the Logic Gates catalog. AND, OR, XOR, and other combinational gate and boolean logic primitives. Marked Easy: a small block you can read, simulate, and synthesize in one sitting.

This IP core implements a fast, combinational 8-bit XOR-reduce tree to compute the parity of an input vector.

It utilizes a hierarchical three-stage binary tree structure to minimize latency, making it suitable for high-speed parity generation and error detection applications.

The design is fully verified with exhaustive and random testing.

  1. Stage 1: Pairs adjacent input bits to produce 4 intermediate signals.
  2. Stage 2: Pairs the Stage 1 outputs to produce 2 signals.
  3. Stage 3: XORs the Stage 2 outputs to produce the final parity result.
  1. Choose Open in IDE. RTL Studio loads the packaged workspace for XOR-Reduce Tree 8-bit.
  2. Read the Verilog module in the editor. The catalog line for this block: An 8-bit XOR-reduce tree that computes the parity of an 8-bit input vector using a hierarchical binary tree structure.
  3. Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
  4. Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Ports

PortDirectionWidthDescription
inInput[7:0]8-bit input vector
outOutput1XOR reduction result (parity)

Architecture

The data flow follows a strict binary tree reduction:

Verification

The IP includes a comprehensive testbench (tb/tb_xor_reduce_tree_8bit.v) that performs:

  • Exhaustive Testing: Checks all $2^8 = 256$ input combinations.
  • Random Testing: Verifies random vectors for robustness.
  • Edge Cases: Specifically tests all-zeros, all-ones, and single-bit set scenarios.

### Test Case Highlights

Test CaseInputExpected OutputDescription
TC18'h000All zeros (Even parity)
TC28'hFF0All ones (Even parity)
TC38'h011Single bit set (Odd parity)
TC48'h801Single bit set (Odd parity)
TC58'h071Odd parity (3 bits set)
TC68'h030Even parity (2 bits set)

Integration

To use this IP in your project:

  1. Include rtl/xor_reduce_tree_8bit.v in your synthesis simulation sources.
  2. Instantiate the module using the port list defined above.

### Example Instantiation

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