Logic Gates
OR-Reduce 8-Bit
Combinational 8-bit OR-reduce gate producing a single output bit.
About this block
Simulate it in the Verilog IDE
OR-Reduce 8-Bit is a Verilog reference block in the Logic Gates catalog. AND, OR, XOR, and other combinational gate and boolean logic primitives. Marked Easy: a small block you can read, simulate, and synthesize in one sitting.
This Intellectual Property (IP) implements a combinational 8-bit OR-reduce gate.
It accepts an 8-bit input vector and produces a single-bit output.
The output is asserted high (1) if any bit in the input vector is high, and low (0) otherwise.
- Functionality: 8-bit OR reduction.
- Type: Combinational logic.
- Implementation: Verilog reduction operator
|. - Verification: Comprehensive testbench covering zero, all-ones, single-bit, and mixed patterns.
- Choose Open in IDE. RTL Studio loads the packaged workspace for OR-Reduce 8-Bit.
- Read the Verilog module in the editor. The catalog line for this block: Combinational 8-bit OR-reduce gate producing a single output bit.
- Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
- Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.
RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.
Ports
| Port | Direction | Width | Description |
|---|---|---|---|
data | Input | [7:0] | 8-bit input vector |
out | Output | 1 | OR-reduced result (1 if any bit in data is 1) |
Architecture
The design uses a single continuous assignment statement to perform the reduction. This ensures minimal critical path delay and optimal resource utilization in FPGA/ASIC implementations.
Verification
The testbench (tb/tb_or_reduce_8bit.v) covers the following critical cases:
| Test Case | Input | Expected Output | Description |
|---|---|---|---|
| TC1 | 0x00 | 0 | All zeros |
| TC2 | 0xFF | 1 | All ones |
| TC3 | 0x01 | 1 | LSB set |
| TC4 | 0x80 | 1 | MSB set |
| TC5 | 0xAB | 1 | Mixed pattern |
| TC6 | 0x55 | 1 | Even bits set |
| TC7 | 0xAA | 1 | Odd bits set |
| TC8 | 0x02 | 1 | Single bit set |
All test cases passed successfully.
More in Logic Gates
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- 2-Input OR Gate
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- 3-State Buffer with Enable and High-Z
- 5-Input Majority Voter with Fault Tolerance
- 8-Bit Bitwise XNOR Gate
- 8-Bit NAND Reduction
- 8-Input Majority Voter
- Bitwise Mask AND/OR 8-bit
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