Logic Gates

2-Input NAND Gate

A basic 2-input NAND gate implemented in Verilog.

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About this block

Simulate it in the Verilog IDE

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2-Input NAND Gate is a Verilog reference block in the Logic Gates catalog. AND, OR, XOR, and other combinational gate and boolean logic primitives. Marked Easy: a small block you can read, simulate, and synthesize in one sitting.

This OpenIP implements a basic 2-input NAND gate using Verilog. It is a fundamental logic gate suitable for educational purposes and basic digital design integration.

This IP provides a verified 2-input NAND gate. It is suitable for basic logic synthesis and simulation. The design is minimal, using a single continuous assignment statement, and includes a comprehensive testbench covering all input combinations.

The module performs the logical NAND operation on two input bits. It outputs a low signal only when both inputs are high.

Choose Open in IDE. RTL Studio loads the packaged workspace for 2-Input NAND Gate.
Read the Verilog module in the editor. The catalog line for this block: A basic 2-input NAND gate implemented in Verilog.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Ports

Port	Direction	Width	Description
a	input	1	First input bit
b	input	1	Second input bit
y	output	1	NAND result

Architecture

The design uses a single continuous assignment statement.

Verification

The testbench verifies all four input combinations.

Test Case	Inputs	Expected Output	Result
TC1	0, 0	1	PASS
TC2	0, 1	1	PASS
TC3	1, 0	1	PASS
TC4	1, 1	0	PASS

All test cases passed successfully.

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