Logic Gates
3-Input Majority Voter
Combinational logic module that outputs the majority value of three binary inputs.
About this block
Simulate it in the Verilog IDE
3-Input Majority Voter is a Verilog reference block in the Logic Gates catalog. AND, OR, XOR, and other combinational gate and boolean logic primitives. Marked Easy: a small block you can read, simulate, and synthesize in one sitting.
The 3-Input Majority Voter determines the majority value of three binary inputs. Output is high if two or more inputs are high. This is a purely combinational logic block.
The 3-Input Majority Voter is a simple, efficient combinational circuit. It correctly identifies the majority value of three binary signals. Simulation confirms correct behavior for all input combinations.
- Choose Open in IDE. RTL Studio loads the packaged workspace for 3-Input Majority Voter.
- Read the Verilog module in the editor. The catalog line for this block: Combinational logic module that outputs the majority value of three binary inputs.
- Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
- Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.
RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.
Architecture
The module implements the boolean expression: out = (a & b) | (b & c) | (a & c). It uses standard AND and OR gates to evaluate the majority condition. No clock or state is required for this operation.
Ports
| Port | Direction | Width | Description |
|---|---|---|---|
| a | Input | 1 | First input bit |
| b | Input | 1 | Second input bit |
| c | Input | 1 | Third input bit |
| out | Output | 1 | Majority result |
Verification
The testbench iterates through all 8 possible input combinations. It checks the output against the expected majority value for each case. All 8 test cases passed successfully in simulation.
| Test Case | Inputs (a,b,c) | Expected | Actual | Status |
|---|---|---|---|---|
| 0 | 0, 0, 0 | 0 | 0 | PASS |
| 1 | 0, 0, 1 | 0 | 0 | PASS |
| 2 | 0, 1, 0 | 0 | 0 | PASS |
| 3 | 0, 1, 1 | 1 | 1 | PASS |
| 4 | 1, 0, 0 | 0 | 0 | PASS |
| 5 | 1, 0, 1 | 1 | 1 | PASS |
| 6 | 1, 1, 0 | 1 | 1 | PASS |
| 7 | 1, 1, 1 | 1 | 1 | PASS |
More in Logic Gates
- 2-Input AND Gate
- 2-Input NAND Gate
- 2-Input NOR Gate
- 2-Input OR Gate
- 2-Input XOR Gate
- 3-Input Bitwise NOR Gate
- 3-State Buffer with Enable and High-Z
- 5-Input Majority Voter with Fault Tolerance
- 8-Bit Bitwise XNOR Gate
- 8-Bit NAND Reduction
- 8-Input Majority Voter
- Bitwise Mask AND/OR 8-bit
- OR-Reduce 8-Bit
- Priority Mask-Below 8-bit
- XOR-Reduce Tree 8-bit