Logic Gates

3-State Buffer with Enable and High-Z

A synchronous 3-state buffer with enable control and active-low reset, outputting High-Z when disabled.

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About this block

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3-State Buffer with Enable and High-Z is a Verilog reference block in the Logic Gates catalog. AND, OR, XOR, and other combinational gate and boolean logic primitives. Marked Easy: a small block you can read, simulate, and synthesize in one sitting.

An OpenIP implementation of a synchronous 3-state buffer with active-low reset and enable control. This module is designed for bus-sharing applications where high-impedance (High-Z) states are required when the buffer is disabled.

This module implements a configurable 8-bit synchronous 3-state buffer. It supports active-low synchronous reset and an enable signal to control data passing versus High-Z output. It is suitable for simple bus interface designs where multiple drivers share a common bus line.

This project is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License (CC-BY-NC-ND-4.0). See the LICENSE file for details.

Choose Open in IDE. RTL Studio loads the packaged workspace for 3-State Buffer with Enable and High-Z.
Read the Verilog module in the editor. The catalog line for this block: A synchronous 3-state buffer with enable control and active-low reset, outputting High-Z when disabled.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

Data Width: 8-bit (fixed in this implementation).
Clocking: Positive edge-triggered synchronous logic.
Reset: Active-low synchronous reset (rst_n).
Control: Enable signal (en) controls data passing vs High-Z state.
Verification: Includes a comprehensive testbench with 5 test cases covering reset, enable, data changes, and disable states.

Ports

Port	Direction	Width	Description
`clk`	Input	1	Clock signal
`rst_n`	Input	1	Active-low reset signal
`data_in`	Input	8	Input data bus
`en`	Input	1	Enable control (1=Drive, 0=High-Z)
`data_out`	Output	8	Output data bus

Verification

The provided testbench (tb/tb_three_state_buffer.v) verifies five key scenarios:

TC1: High-Z output when disabled after reset.
TC2: Data driving when enabled (data_in = 8'h55).
TC3: Data changes while enabled (data_in = 8'hFF).
TC4: Return to High-Z when disabled.
TC5: High-Z output during reset assertion.

### Running Simulation

Ensure you have a Verilog simulator installed (e.g., ModelSim, VCS, or Icarus Verilog).
Navigate to the project root directory.
Run the simulation script or command appropriate for your toolchain.
Check the Log panel for the following expected results:

- TC1 PASS - Output is High-Z - TC2 PASS - Output drives 55h - TC3 PASS - Output drives FFh - TC4 PASS - Output returns to High-Z - TC5 PASS - Output is High-Z on reset - Simulation ends with INFO: PASS

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