Logic Gates
Bitwise Mask AND/OR 8-bit
An 8-bit combinational logic module that performs bitwise AND or OR operations based on a mode select signal.
About this block
Simulate it in the Verilog IDE
Bitwise Mask AND/OR 8-bit is a Verilog reference block in the Logic Gates catalog. AND, OR, XOR, and other combinational gate and boolean logic primitives. Marked Easy: a small block you can read, simulate, and synthesize in one sitting.
This IP implements an 8-bit bitwise logic unit supporting both AND and OR operations. The operation is selected via a single mode control signal.
This module provides a simple and efficient way to perform bitwise masking operations. It is suitable for applications requiring dynamic data filtering or modification.
- Choose Open in IDE. RTL Studio loads the packaged workspace for Bitwise Mask AND/OR 8-bit.
- Read the Verilog module in the editor. The catalog line for this block: An 8-bit combinational logic module that performs bitwise AND or OR operations based on a mode select signal.
- Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
- Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.
RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.
Features
- Supports 8-bit data and mask inputs.
- Selectable bitwise AND or OR operation.
- Combinational logic with zero latency.
- Simple interface suitable for datapath integration.
Ports
| Port | Direction | Width | Description |
|---|---|---|---|
| data | input | 8 | Data input vector |
| mask | input | 8 | Mask input vector |
| mode | input | 1 | Operation select (0=AND, 1=OR) |
| y | output | 8 | Result output vector |
Verification
The testbench covers all functional modes and edge cases.
| Test Case | Description | Expected Result | Status |
|---|---|---|---|
| TC1 | Mode 0, mask 0x00 | y = 0x00 | PASS |
| TC2 | Mode 0, mask 0xFF | y = data | PASS |
| TC3 | Mode 0, partial mask | y = 0x0F | PASS |
| TC4 | Mode 1, mask 0x00 | y = data | PASS |
| TC5 | Mode 1, mask 0xFF | y = 0xFF | PASS |
| TC6 | Mode 1, partial mask | y = 0xF0 | PASS |
| TC7 | Mode 1, mixed data/mask | y = 0xFF | PASS |
| TC8 | Mode 0, mixed data/mask | y = 0x00 | PASS |
All 8 test cases passed successfully. Simulation waveform data is available in sim/dump.vcd.
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