Interface Protocols

Sticky Button Set/Clear Flag

A registered sticky flag module with set and clear inputs where clear takes priority.

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About this block

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Sticky Button Set/Clear Flag is a Verilog reference block in the Interface Protocols catalog. UART, SPI, I2C, and other serial or peripheral protocol interfaces. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This IP implements a registered sticky flag with set and clear inputs.

The flag is set when the set signal is asserted.

The flag is cleared when the clr signal is asserted.

Choose Open in IDE. RTL Studio loads the packaged workspace for Sticky Button Set/Clear Flag.
Read the Verilog module in the editor. The catalog line for this block: A registered sticky flag module with set and clear inputs where clear takes priority.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

Registered Output: Synchronous state update on clock edge.
Priority Logic: clr overrides set if both are active.
Active-Low Reset: Synchronous reset to 0 on rst_n assertion.
Simple Interface: Minimal port count for easy integration.

Interface

The module exposes the following ports:

Port	Direction	Width	Description
clk	Input	1	Clock input
rst_n	Input	1	Active-low reset
set	Input	1	Set flag command
clr	Input	1	Clear flag command
flag	Output	1	Sticky flag status

Architecture

The design uses a single D-type flip-flop to store the flag state. The logic prioritizes the clear signal over the set signal.

Verification

The testbench verifies the following scenarios:

Test Case	Description	Expected Result
TC1	Reset clears flag	`flag` is 0
TC2	Set sets flag	`flag` is 1
TC3	Sticky hold	`flag` remains 1
TC4	Clear clears flag	`flag` is 0
TC5	Set and Clear active	`clr` wins, `flag` is 0

All tests passed successfully.

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