SPI Mode-0 Host (8-Bit Frames)

Features

• SPI Mode 0 Support: Implements standard SPI Mode 0 (Idle Low, Sample on Rising Edge).
• 8-Bit Data Width: Transfers 8-bit data words MSB-first.
• Parameterizable Clock: Configurable CLK_DIV parameter to adjust SCK frequency relative to clk.
• Synchronous Design: Uses a synchronous state machine for reliable timing and easy integration.
• Verified: Includes a comprehensive self-checking testbench with waveform dump support.

Ports

Port Name	Direction	Width	Description
clk	Input	1	System clock input
rst_n	Input	1	Active-low asynchronous reset
start	Input	1	Start transfer pulse (single cycle)
tx_data	Input	8	Data to transmit
done	Output	1	Transfer complete flag (high during DONE state)
rx_data	Output	8	Received data
sck	Output	1	SPI clock output
mosi	Output	1	Master Out Slave In
miso	Input	1	Master In Slave Out

Architecture

The design is composed of three main blocks:

1. Clock Divider: Generates the SPI bit clock (sck) from the system clock (clk) based on the CLK_DIV parameter.
2. State Machine: Controls the transfer sequence through three states: IDLE, SHIFT, and DONE_S.
3. Shift Register Logic: Handles data loading, shifting out on mosi, and sampling from miso.

### Data Flow

• Data is loaded into the shift register when start is asserted.
• Bits are shifted out MSB-first on mosi.
• Bits are sampled from miso on the rising edge of sck.
• The done signal asserts when the transfer is complete.

Verification

The included testbench (tb_simple_spi_host.v) verifies functional correctness.

### Test Cases

Test Case	TX Data	MISO Data	Expected RX	Result
TC1	0x55	0x55	0x55	PASS
TC2	0xAA	0xAA	0xAA	PASS
TC3	0x00	0x00	0x00	PASS
TC4	0xFF	0xFF	0xFF	PASS
TC5	0xAB	0xAB	0xAB	PASS
TC6	0x00	0xFF	0xFF	PASS
TC7	0xFF	0x00	0x00	PASS

### Running Simulation

1. Run the simulation in your preferred EDA tool.
2. Check the log output for INFO: PASS.
3. Inspect sim/dump.vcd using the waveform viewer for timing analysis.

### Expected Log Output

Integration

• Chip Select: This IP does not handle chip select (CS); you must manage CS externally to ensure the slave is selected during the transfer.
• Timing Constraints: Ensure setup and hold times for the external miso signal relative to sck are met by the slave device.
• Reset Synchronization: The rst_n is asynchronous. Ensure your system reset logic synchronizes rst_n if crossing clock domains.
• Start Signal: The start signal should be a single-cycle pulse. If held high, the controller may initiate multiple transfers depending on implementation details; it is recommended to de-assert start immediately after assertion.