Interface Protocols

SPI Master Lite

Minimal SPI master for CPOL=0, CPHA=0, 8-bit transfers with start/done handshake.

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About this block

Simulate it in the Verilog IDE

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SPI Master Lite is a Verilog reference block in the Interface Protocols catalog. UART, SPI, I2C, and other serial or peripheral protocol interfaces. Marked Hard: a larger reference. Simulate the packaged testbench before you change the RTL.

This IP implements a minimal SPI master controller for CPOL=0 and CPHA=0 modes. It supports 8-bit data transfers with a simple start and done handshake interface. The module shifts data out MSB first while capturing MISO data simultaneously.

This IP provides a lightweight SPI master for simple 8-bit communication. It is suitable for applications requiring minimal logic resource usage. The design is fully verified with a comprehensive testbench. Use the RtlStudio Waveform tab to inspect signal timing with sim/dump.vcd.

Choose Open in IDE. RTL Studio loads the packaged workspace for SPI Master Lite.
Read the Verilog module in the editor. The catalog line for this block: Minimal SPI master for CPOL=0, CPHA=0, 8-bit transfers with start/done handshake.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

The design operates with a single clock and active-low reset signal. It asserts a busy flag during the entire transfer duration. CS_N is automatically driven low during the transfer and high when idle. SCK is generated internally to clock data out on the rising edge. MISO data is sampled on the rising edge of SCK. The controller completes an 8-bit transfer in a fixed number of clock cycles.

Ports

Port Name	Direction	Width	Description
clk	Input	1	System clock input
rst_n	Input	1	Asynchronous active-low reset
start	Input	1	Pulse to initiate an 8-bit transfer
mosi_data	Input	8	Data to be transmitted on MOSI
miso	Input	1	Serial data input from slave
busy	Output	1	High during transfer, low when idle
done	Output	1	High for one cycle after transfer completes
miso_data	Output	8	Captured data from MISO line
sck	Output	1	Serial clock output
cs_n	Output	1	Chip select output (active low)
mosi	Output	1	Serial data output

Architecture

The controller uses a finite state machine with three states. The IDLE state waits for the start signal to initiate a transfer. The SHIFT_SETUP state prepares the shift register for the next bit. The SHIFT_SAMPLE state shifts data out and captures MISO input.

Verification

The testbench performs a loopback connection where MISO mirrors MOSI. Ten test cases verify basic data transfer and signal integrity. Test Case 1 transfers 0x55 and verifies the received data matches. Test Case 2 transfers 0x00 and verifies the received data matches. Test Case 3 transfers 0xFF and verifies the received data matches. Test Case 4 transfers 0xAA and verifies the received data matches. Test Case 5 transfers 0x55 again to ensure repeatability. Test Case 6 verifies that CS_N is active low during the transfer. Test Case 7 verifies that the busy signal is asserted correctly. Test Case 8 verifies that the done signal is asserted correctly. Test Case 9 performs two rapid successive transfers to check state recovery. Test Case 10 verifies transfer completion with a mismatched MISO input. All ten test cases passed successfully in the simulation log.

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