Interface Protocols

1-Bit GPIO Pin Driver (Combinational) — L1 Upgrade — L2 Upgrade

A 1-bit GPIO pin driver that detects edge transitions and generates a sticky interrupt flag.

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About this block

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Mediumverilogsimsyn

1-Bit GPIO Pin Driver (Combinational) — L1 Upgrade — L2 Upgrade is a Verilog reference block in the Interface Protocols catalog. UART, SPI, I2C, and other serial or peripheral protocol interfaces. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This IP core implements a robust 1-bit GPIO pin driver with sticky interrupt detection. It monitors the gpio_in signal for both rising and falling edges, generating an irq_sticky flag that remains asserted until explicitly cleared by the irq_clear signal. This ensures that transient events are never missed, making it ideal for embedded systems requiring reliable event logging or interrupt handling.

The design utilizes synchronous logic for edge detection and interrupt latching, ensuring deterministic behavior and compatibility with standard synchronous design flows.

Choose Open in IDE. RTL Studio loads the packaged workspace for 1-Bit GPIO Pin Driver (Combinational) — L1 Upgrade — L2 Upgrade.
Read the Verilog module in the editor. The catalog line for this block: A 1-bit GPIO pin driver that detects edge transitions and generates a sticky interrupt flag.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

Edge Detection: Detects both rising and falling edges on the gpio_in signal.
Sticky Interrupt: The irq_sticky flag remains asserted until cleared, ensuring no interrupt is missed.
Asynchronous Clear: Supports an active-high irq_clear signal to reset the interrupt flag.
Synchronous Reset: Ensures deterministic initialization via an active-low rst_n signal.
Efficient Logic: Uses minimal resources with a single delay register for edge comparison.

Interface

The module uses the following ports:

Port Name	Direction	Width	Description
`clk`	Input	1	System clock input
`rst_n`	Input	1	Active-low asynchronous reset
`gpio_in`	Input	1	GPIO pin input signal
`irq_clear`	Input	1	Active-high signal to clear sticky interrupt
`irq_sticky`	Output	1	Sticky interrupt flag (high when edge detected)

Architecture

The design consists of two main components:

Edge Detector: A flip-flop (gpio_dly) delays the gpio_in signal by one clock cycle. A comparator checks for differences between the current gpio_in and the delayed value.
Sticky Latch: A second flip-flop latches the irq_sticky flag. It is set when a transition is detected and cleared when irq_clear is asserted or rst_n is active.

Verification

The testbench verifies the following scenarios:

Test Case	Description	Expected Result
TC1	Reset behavior	`irq_sticky` is 0
TC2	No change, no IRQ	`irq_sticky` remains 0
TC3	Rising edge detection	`irq_sticky` becomes 1
TC4	Falling edge detection	`irq_sticky` remains 1
TC5	Clear IRQ	`irq_sticky` becomes 0
TC6	Re-trigger after clear	`irq_sticky` becomes 1

Run the simulation to verify all test cases pass. The simulation log should confirm INFO: PASS for all tests.

### Expected Results

After Run Simulation, the Log panel should show:

TC1 PASS Reset check
TC2 PASS No change check
TC3 PASS Rising edge check
TC4 PASS Falling edge sticky check
TC5 PASS Clear check
TC6 PASS Re-trigger check
Simulation ends with INFO: PASS.

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