Interface Protocols

I2C Arbitration Lost Detector

Detects I2C arbitration loss by comparing driven and sampled SDA values. Outputs a sticky flag until cleared.

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About this block

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I2C Arbitration Lost Detector is a Verilog reference block in the Interface Protocols catalog. UART, SPI, I2C, and other serial or peripheral protocol interfaces. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This IP provides a robust mechanism for detecting I2C arbitration loss.

It adheres to the I2C specification for open-drain bus monitoring.

The sticky flag ensures that the event is not missed by the controller.

Choose Open in IDE. RTL Studio loads the packaged workspace for I2C Arbitration Lost Detector.
Read the Verilog module in the editor. The catalog line for this block: Detects I2C arbitration loss by comparing driven and sampled SDA values. Outputs a sticky flag until cleared.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

Arbitration Loss Detection: Detects when SDA is driven low but sampled high.
Sticky Flag: The arb_lost signal remains asserted until explicitly cleared.
Flexible Reset: Supports both asynchronous active-low reset (rst_n) and synchronous active-high clear (clr).
Low Latency: Combinational comparison with synchronous latching.

Ports

Port Name	Direction	Width	Description
clk	Input	1	Clock input
rst_n	Input	1	Active-low asynchronous reset
sda_in	Input	1	Sampled SDA line value
sda_drive	Input	1	Value driven onto SDA line
clr	Input	1	Active-high clear signal
arb_lost	Output	1	Sticky arbitration lost flag

Architecture

The following block diagram illustrates the internal logic flow.

The core logic compares the driven value against the sampled value. If the driven value is low and the sampled value is high, the flag sets. The flag is sticky and does not clear automatically when the condition ends. An asynchronous reset clears the flag to zero. An active-high clear signal also resets the flag synchronously.

Verification

The testbench verifies normal operation and arbitration loss scenarios. It checks that the flag remains zero during normal driving conditions. It confirms detection when driving low and sampling high. It validates the sticky behavior after the condition clears. It ensures the clear signal resets the flag correctly. It verifies the asynchronous reset functionality.

Test Case	Condition	Expected Result	Status
TC1	Drive H, Sample H	arb_lost = 0	PASS
TC2	Drive L, Sample L	arb_lost = 0	PASS
TC3	Drive L, Sample H	arb_lost = 1	PASS
TC4	Condition Removed	arb_lost = 1 (Sticky)	PASS
TC5	Clear Asserted	arb_lost = 0	PASS
TC6	Reset Asserted	arb_lost = 0	PASS

All six test cases passed successfully. The simulation log confirms correct behavior for all scenarios. No errors were reported during the test run.

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