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Interface Protocols

8-Bit GPIO Set/Clear Register

An 8-bit GPIO register with atomic Set and Clear operations where Clear takes priority over Set.

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About this block

Simulate it in the Verilog IDE

Mediumverilogsimsyn

8-Bit GPIO Set/Clear Register is a Verilog reference block in the Interface Protocols catalog. UART, SPI, I2C, and other serial or peripheral protocol interfaces. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This IP implements an 8-bit General Purpose Input/Output (GPIO) register designed for atomic Set and Clear operations. It provides a standard, low-latency interface for controlling GPIO pins in embedded systems.

A key feature of this design is that Clear operations take precedence over Set operations within the same clock cycle. This effectively prevents race conditions when updating pin states concurrently. The module is synchronous, uses an active-low reset, and is suitable for simple GPIO control tasks without the overhead of complex state machines.

  1. Choose Open in IDE. RTL Studio loads the packaged workspace for 8-Bit GPIO Set/Clear Register.
  2. Read the Verilog module in the editor. The catalog line for this block: An 8-bit GPIO register with atomic Set and Clear operations where Clear takes priority over Set.
  3. Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
  4. Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

  • 8-Bit Parallel Data Width: Supports control of 8 independent GPIO pins.
  • Atomic Set/Clear: Separate set_mask and clr_mask inputs allow simultaneous updates.
  • Clear Priority: If a bit is specified in both set_mask and clr_mask, the Clear operation dominates, forcing the bit to 0.
  • Synchronous Reset: Active-low reset (rst_n) forces all output bits to 0 on the next clock edge.
  • Low Latency: Combinatorial output logic ensures minimal propagation delay.

Ports

Port NameDirectionWidthDescription
clkInput1Clock input. Updates occur on the positive edge.
rst_nInput1Active-low synchronous reset.
set_maskInput[7:0]Mask bits to set to logic 1.
clr_maskInput[7:0]Mask bits to set to logic 0.
doutOutput[7:0]Current state of the GPIO register.

Architecture

The internal logic implements a priority-based update scheme. The output dout is updated on the positive edge of the clock. The logic equation is:

This equation ensures that:

  1. Bits in clr_mask are forced to 0 (Clear Priority).
  2. Bits in set_mask are forced to 1.
  3. Bits not in either mask retain their previous state.

### Block Diagram

Verification

The provided testbench (tb/tb_gpio_set_clr_8.v) verifies five key scenarios to ensure functional correctness:

  1. Reset Check: Verifies that rst_n clears all output bits to zero.
  2. Set Check: Verifies that set_mask correctly sets bits to 1.
  3. Clear Check: Verifies that clr_mask correctly clears bits to 0.
  4. Priority Check: Verifies that simultaneous Set and Clear operations result in Clear (0).
  5. Re-set Check: Verifies that bits previously cleared can be set again.

### Expected Simulation Results

After running the simulation, the log panel should display:

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