Interface Protocols

I2C Start/Stop Detector

Detects I2C Start and Stop conditions synchronously on the SCL rising edge.

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About this block

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I2C Start/Stop Detector is a Verilog reference block in the Interface Protocols catalog. UART, SPI, I2C, and other serial or peripheral protocol interfaces. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This IP core detects I2C Start and Stop conditions on the SDA and SCL lines. It operates synchronously to the SCL rising edge, outputting a pulse when a Start condition (SDA High-to-Low while SCL High) or a Stop condition (SDA Low-to-High while SCL High) is detected.

The design is fully synchronous and suitable for integration into I2C master or slave controllers.

Choose Open in IDE. RTL Studio loads the packaged workspace for I2C Start/Stop Detector.
Read the Verilog module in the editor. The catalog line for this block: Detects I2C Start and Stop conditions synchronously on the SCL rising edge.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Interface

The module has four ports as defined in the table below.

Port Name	Direction	Width	Description
`sda_i`	Input	1	I2C Data Line
`scl_i`	Input	1	I2C Clock Line
`start_o`	Output	1	Active High when Start condition is detected
`stop_o`	Output	1	Active High when Stop condition is detected

Architecture

The detector operates synchronously to the SCL rising edge. It samples the SDA line on each rising edge of SCL. A Start condition is identified when SDA transitions from High to Low while SCL is High. A Stop condition is identified when SDA transitions from Low to High while SCL is High.

Verification

The testbench verifies the following scenarios:

Test Case	Description	Expected Result
TC1	Idle State Check	Both outputs are Low
TC2	Start Condition	`start_o` goes High
TC3	Stop Condition	`stop_o` goes High
TC4	No Detection on SCL Low	Both outputs remain Low
TC5	Reset Functionality	Outputs return to Idle state

All tests passed successfully in the simulation log.

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