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Interface Protocols

I2C Bus Idle Timeout

Detects I2C bus idle conditions based on SCL and SDA levels with configurable threshold.

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About this block

Simulate it in the Verilog IDE

Mediumverilogsimsyn

I2C Bus Idle Timeout is a Verilog reference block in the Interface Protocols catalog. UART, SPI, I2C, and other serial or peripheral protocol interfaces. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This IP core detects when an I2C bus remains idle for a configurable number of clock cycles. It monitors the SCL and SDA lines for the I2C idle state (both high) and asserts a flag when the idle duration exceeds a user-defined threshold.

The design is fully synchronous, synthesizable, and verified using Icarus Verilog.

This IP core provides a robust mechanism for detecting I2C bus idle conditions using a configurable saturating counter. It is designed for easy integration into larger systems, offering clear ports for clock, reset, I2C lines, and configuration. The design is fully verified with a testbench that covers reset, counting, activity detection, and re-accumulation scenarios.

  1. Choose Open in IDE. RTL Studio loads the packaged workspace for I2C Bus Idle Timeout.
  2. Read the Verilog module in the editor. The catalog line for this block: Detects I2C bus idle conditions based on SCL and SDA levels with configurable threshold.
  3. Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
  4. Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

  • Idle Detection: Monitors SCL and SDA lines for the I2C idle condition (SCL=1, SDA=1).
  • Configurable Threshold: Allows setting the idle timeout via a 4-bit input (threshold_i).
  • Saturating Counter: Prevents counter overflow by saturating at the threshold value.
  • Activity Reset: Immediately resets the counter and idle flag upon any bus activity (SCL=0 or SDA=0).
  • Synthesizable: Designed for standard CMOS synthesis flows.

Ports

Port NameDirectionWidthDescription
clkinput1System clock input
rst_ninput1Active-low asynchronous reset
scl_iinput1I2C Serial Clock line
sda_iinput1I2C Serial Data line
threshold_iinput[3:0]Idle cycle threshold (0-15)
idle_ooutput1High when idle count >= threshold
count_ooutput[3:0]Current idle cycle count

Architecture

The module uses a synchronous counter to track consecutive cycles where both SCL and SDA are high.

  1. Reset: On rst_n low, count_o and idle_o are reset to 0.
  2. Idle Condition: If scl_i and sda_i are both high, the counter increments.
  3. Saturation: If count_o reaches threshold_i, it stays saturated at that value.
  4. Activity: If either scl_i or sda_i goes low, the counter resets to 0 and idle_o deasserts.
  5. Output: idle_o asserts high when count_o >= threshold_i.

Verification

### Prerequisites

Install [Icarus Verilog](https://iverilog.icarus.com/).

### Running Simulation

### Expected Output

  1. Reset Behavior: Ensures outputs are zero after reset.
  2. Count Accumulation: Verifies counter increments during idle.
  3. Activity Reset: Confirms counter resets on bus activity.
  4. Re-accumulation: Checks counter resumes counting after activity stops.

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