Interface Protocols

8-Bit GPIO with Direction and Rising-Edge IRQ

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About this block

Simulate it in the Verilog IDE

Mediumverilogsimsyn

8-Bit GPIO with Direction and Rising-Edge IRQ is a Verilog reference block in the Interface Protocols catalog. UART, SPI, I2C, and other serial or peripheral protocol interfaces. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This module implements an 8-bit General Purpose Input/Output (GPIO) controller. It supports register-mapped read and write access via a 4-bit address bus. The controller allows independent input or output direction configuration per pin. It features edge-triggered interrupt generation for rising edges.

This 8-bit GPIO controller provides a simple and effective way to manage digital I/O pins. It supports independent direction control and edge-triggered interrupts for efficient event handling. The register-mapped interface allows easy integration with standard bus protocols. Integrators can rely on the verified testbench to ensure correct functionality in their designs.

Choose Open in IDE. RTL Studio loads the packaged workspace for 8-Bit GPIO with Direction and Rising-Edge IRQ.
Read the Verilog module in the editor. The catalog line for this block: Register-mapped 8-bit GPIO with per-pin direction, data registers, and rising-edge interrupt generation.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

8-bit Data Register: Stores input/output values.
8-bit Direction Register: Configures per-pin direction (Input/Output).
8-bit Interrupt Enable Register (IE): Enables interrupt generation for specific pins.
8-bit Interrupt Clear Register (ICR): Write-only register to clear interrupt status bits.
Rising Edge Detection: Generates interrupt signals on rising edges of input pins.
Single Interrupt Output: Aggregates interrupts from all enabled pins into a single irq line.

Interface

The module uses the following ports:

Port Name	Direction	Width	Description
`clk`	Input	1	Clock input
`rst_n`	Input	1	Active-low reset
`addr`	Input	4	Register address bus
`wr_en`	Input	1	Write enable signal
`wr_data`	Input	8	Write data bus
`rd_data`	Output	8	Read data bus
`gpio_in`	Input	8	External GPIO input pins
`gpio_out`	Output	8	External GPIO output pins
`irq`	Output	1	Interrupt request signal

Architecture

The following diagram illustrates the internal data flow and control logic.

Verification

The testbench tb/tb_gpio_8b.v verifies the following scenarios:

Test Case	Description	Status
TC1	Basic Readback of Reset Values	PASS
TC2	Direction Change and Passthrough	PASS
TC3	Write-Read Data Integrity	PASS
TC4	Interrupt Assert on Rising Edge	PASS
TC5	Interrupt Clear via ICR	PASS
TC6	Interrupt Disable Functionality	PASS

All tests passed successfully in Icarus Verilog simulation.

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