RTL Studio Open IDE

Interface Protocols

I2C NACK Sticky Flag Detector

Detects I2C NACK conditions during the ACK phase and latches a sticky flag until reset.

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About this block

Simulate it in the Verilog IDE

Mediumverilogsimsyn

I2C NACK Sticky Flag Detector is a Verilog reference block in the Interface Protocols catalog. UART, SPI, I2C, and other serial or peripheral protocol interfaces. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This IP core detects I2C NACK conditions during the ACK phase of a byte transfer.

It provides two outputs: an immediate detection flag (nack_detected) and a sticky flag (nack_sticky_flag) that latches the NACK event until explicitly reset.

This module is designed for integration into I2C controllers or bus monitors to handle error conditions robustly.

  • Detection: Asserts nack_detected when SDA is high (NACK) at the end of a byte transfer.
  • Latching: Asserts nack_sticky_flag to latch the NACK condition. This flag remains asserted until a synchronous reset clears it.
  1. Normal ACK: If is_ack_phase is high, byte_complete is high, and sda is low, both flags remain low (or clear if previously set).
  2. NACK Event: If is_ack_phase is high, byte_complete is high, and sda is high, nack_detected goes high immediately. nack_sticky_flag also goes high and stays high.
  3. Reset: An active-low rst_n clears both nack_detected and nack_sticky_flag to 0.
  1. Choose Open in IDE. RTL Studio loads the packaged workspace for I2C NACK Sticky Flag Detector.
  2. Read the Verilog module in the editor. The catalog line for this block: Detects I2C NACK conditions during the ACK phase and latches a sticky flag until reset.
  3. Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
  4. Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Ports

Port NameDirectionWidthDescription
clkInput1Clock input
rst_nInput1Active-low synchronous reset
sdaInput1I2C SDA line status
byte_completeInput1Indicates end of 9th clock cycle
is_ack_phaseInput1Indicates current phase is ACK
nack_sticky_flagOutput1Latched NACK indicator
nack_detectedOutput1Immediate NACK detection

Verification

The testbench covers the following scenarios:

Test CaseDescriptionExpected Result
TC1ACK Case - SDA Low during ACK phasenack_detected is 0
TC2NACK Case - SDA High during ACK phasenack_detected is 1, nack_sticky_flag is 1
TC3Sticky Flag Persistencenack_sticky_flag remains 1 after inputs clear
TC4Reset Clears Sticky FlagBoth flags clear to 0 on reset

### Running the Simulation

  1. Ensure you have a Verilog simulator installed (e.g., Icarus Verilog, ModelSim, or Vivado).
  2. Navigate to the project root directory.
  3. Run the simulation script or command provided in the Makefile or simulation instructions.
  4. Check the Log panel for the following output:

- TC1 PASS - ACK case correct - TC2 PASS - NACK case correct - TC2 Sticky PASS - TC3 PASS - Sticky flag persisted - TC4 PASS - Reset cleared sticky flag - TC4 Detected Clear PASS - Simulation ends with INFO: PASS.

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