Interface Protocols

JTAG TAP Controller

Synthesizable IEEE 1149.1 JTAG TAP Controller with 32-bit DR and IR paths.

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About this block

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Hardverilogsimsyn

JTAG TAP Controller is a Verilog reference block in the Interface Protocols catalog. UART, SPI, I2C, and other serial or peripheral protocol interfaces. Marked Hard: a larger reference. Simulate the packaged testbench before you change the RTL.

A synthesizable, IEEE 1149.1 compliant JTAG TAP (Test Access Port) Controller IP core. This module implements the standard 16-state Finite State Machine (FSM) required for boundary scan operations, supporting both Data Register (DR) and Instruction Register (IR) shift paths.

This IP provides a robust, synthesizable JTAG TAP Controller designed for integration into larger SoC designs requiring standard JTAG connectivity.

It handles all standard JTAG states, including Test-Logic-Reset, Run-Test-Idle, and all Scan states for DR and IR.

Choose Open in IDE. RTL Studio loads the packaged workspace for JTAG TAP Controller.
Read the Verilog module in the editor. The catalog line for this block: Synthesizable IEEE 1149.1 JTAG TAP Controller with 32-bit DR and IR paths.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

IEEE 1149.1 Compliance: Full implementation of the 16-state JTAG TAP FSM.
Register Paths:

- 32-bit Data Register (DR) with IDCODE capture support. - 32-bit Instruction Register (IR) with shift and update logic.

Reset Mechanisms:

- Synchronous reset via rst_n. - Asynchronous TAP reset via trst_n.

Standard Interface: Exposes standard JTAG pins: TCK, TMS, TDI, and TDO.
Output Interfaces: Provides parallel outputs for updated DR (dr_out) and IR (ir_out) values for internal SoC use.
Synthesizable: Verilog-2001 compatible source code.

Ports

Port Name	Direction	Width	Description
`clk`	Input	1	System clock input
`rst_n`	Input	1	Active-low synchronous reset
`tms`	Input	1	Test Mode Select input
`tck`	Input	1	Test Clock input
`trst_n`	Input	1	Active-low Test Reset input (Asynchronous)
`idcode`	Input	32	IDCODE value loaded into DR during Capture-DR
`tdi`	Input	1	Test Data Input shifted into registers
`dr_out`	Output	32	Updated Data Register output
`ir_out`	Output	32	Updated Instruction Register output
`tdo`	Output	1	Test Data Output shifted out from registers

Verification

The provided testbench tb_jtag_tap_controller.v validates the core functionality.

### Test Scenarios

Test Case	Description	Expected Result
TC1	Initial Reset State	Module enters Run-Test-Idle after reset
TC2	DR Shift Operation	Shift in zeros results in `dr_out` being zero after Update-DR
TC3	IR Shift Operation	Shift in zeros results in `ir_out` being zero after Update-IR

### Running the Simulation

Prerequisites: Ensure you have a Verilog simulator installed (e.g., ModelSim, VCS, or Icarus Verilog).
Execute: Run the simulation script provided in the root directory (e.g., run_sim.sh or equivalent).
Verify: Check the Log panel for pass indicators. Typical output includes:

- TC2 PASS DR_OUT matches - TC3 PASS IR_OUT matches - Simulation ends with INFO: PASS

Waveforms: Use your simulator's waveform viewer to inspect signal transitions using the generated dump file (e.g., sim/dump.vcd).

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