Interface Protocols

I2C Clock Stretch Detector

Detects I2C clock stretching by counting SCL low cycles against a configurable threshold.

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I2C Clock Stretch Detector is a Verilog reference block in the Interface Protocols catalog. UART, SPI, I2C, and other serial or peripheral protocol interfaces. Marked Hard: a larger reference. Simulate the packaged testbench before you change the RTL.

This IP core provides a robust, configurable mechanism for detecting I2C clock stretching. By monitoring the SCL line and comparing the low duration against a user-defined threshold, it enables master controllers to gracefully handle slow slaves or bus contention. The synchronous design ensures easy integration into existing FPGA/ASIC designs, and the dual output flags allow for both event detection and active state monitoring.

Choose Open in IDE. RTL Studio loads the packaged workspace for I2C Clock Stretch Detector.
Read the Verilog module in the editor. The catalog line for this block: Detects I2C clock stretching by counting SCL low cycles against a configurable threshold.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

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