Interface Protocols

8-Bit GPIO Output Register

8-Bit GPIO Output Register with synchronous load and active-low reset

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About this block

Simulate it in the Verilog IDE

Mediumverilogsimsyn

8-Bit GPIO Output Register is a Verilog reference block in the Interface Protocols catalog. UART, SPI, I2C, and other serial or peripheral protocol interfaces. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This IP core implements a simple, synchronous 8-bit General Purpose Input/Output (GPIO) output register. It is designed for low-latency control interfaces where data is latched only when a write enable signal is asserted.

Key Features:

Synchronous data loading on the positive clock edge.
Active-low asynchronous reset (rst_n) that forces output to zero.
Simple 5-port interface for easy integration.

Choose Open in IDE. RTL Studio loads the packaged workspace for 8-Bit GPIO Output Register.
Read the Verilog module in the editor. The catalog line for this block: 8-Bit GPIO Output Register with synchronous load and active-low reset.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Architecture

The design consists of a single register stage. Data is latched on the positive edge of the clock when the write enable (we) is high. An active-low reset (rst_n) forces the output to zero immediately, overriding any data loading operations.

Ports

Port Name	Direction	Width	Description
`clk`	Input	1	Clock input
`rst_n`	Input	1	Active-low asynchronous reset
`we`	Input	1	Write enable (synchronous load)
`din`	Input	8	Data input
`dout`	Output	8	Data output

Verification

The provided testbench (tb/tb_gpio_out_reg_8.v) verifies the following behaviors:

Reset Priority: Output is zero when reset is active.
Data Loading: Output updates to input data on clock edge when we is high.
Hold State: Output retains value when we is low.
Data Update: Output updates to new data when we is asserted again.
Reset During Load: Reset overrides data loading immediately.

### Running Simulation

To run the simulation using Icarus Verilog:

### Expected Results

INFO: TC1 PASS reset check
INFO: TC2 PASS load check
INFO: TC3 PASS hold check
INFO: TC4 PASS load new data check
INFO: TC5 PASS reset during load check
Simulation ends with INFO: PASS

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