Interface Protocols

32-Bit MMIO GPIO (DI Read, Byte-Strobed DO) — L2 Upgrade

32-Bit MMIO GPIO with byte-strobed data output and sticky pin-change interrupt.

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About this block

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32-Bit MMIO GPIO (DI Read, Byte-Strobed DO) — L2 Upgrade is a Verilog reference block in the Interface Protocols catalog. UART, SPI, I2C, and other serial or peripheral protocol interfaces. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This IP implements a 32-bit General Purpose Input/Output (GPIO) interface with Memory-Mapped I/O (MMIO). It supports reading external pin states and writing to internal data registers with byte-level granularity.

A key feature is a sticky interrupt request (IRQ) flag that asserts whenever external input pins differ from the stored data register value. This flag must be explicitly cleared via a control register write, ensuring that pin state changes are not missed by the processor.

Choose Open in IDE. RTL Studio loads the packaged workspace for 32-Bit MMIO GPIO (DI Read, Byte-Strobed DO) — L2 Upgrade.
Read the Verilog module in the editor. The catalog line for this block: 32-Bit MMIO GPIO with byte-strobed data output and sticky pin-change interrupt.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

32-bit Data Bus: Supports full 32-bit data input and output operations.
Byte-Level Write Control: Uses a 4-bit byte_strobe mask to selectively update individual 8-bit segments of the internal data register.
Sticky Interrupt: Asserts irq high when gpio_in differs from gpio_data. Remains high until cleared by writing to the control register.
Asynchronous Reset: Initializes all internal registers to zero on rst_n assertion.
L2 Integration Ready: Designed for seamless integration into L2 system architectures.

Ports

Port Name	Direction	Width	Description
`clk`	Input	1	Clock signal
`rst_n`	Input	1	Active-low asynchronous reset
`addr`	Input	5	Memory-mapped address bus
`wr_en`	Input	1	Write enable signal
`data_in`	Input	32	Data input from bus
`byte_strobe`	Input	4	Byte write enable mask `[3:0]`
`gpio_in`	Input	32	External GPIO pin inputs
`data_out`	Output	32	Internal data register output
`irq`	Output	1	Sticky interrupt request flag

Architecture

The module consists of an internal 32-bit data register (gpio_data) and a 1-bit sticky flag (irq_sticky).

### Address Map

Address	Register	Description
`5'h00`	Data Register	Read/Write. Updates `gpio_data` based on `byte_strobe`.
`5'h1F`	Control Register	Write-Only. Clears `irq_sticky` to 0.

### Logic Flow

Data Update: On wr_en and addr == 5'h00, gpio_data is updated byte-by-byte based on byte_strobe.
IRQ Clear: On wr_en and addr == 5'h1F, irq_sticky is cleared to 0.
IRQ Assert: Combinational logic compares gpio_in with gpio_data. If they differ, irq_sticky is set to 1.

Integration

Import: Add the RTL file rtl/gpio_mmio_32bit_byte_strobed_pin_change_sticky.v to your project.
Connect: Map the ports according to the table above.
Constraints: Ensure clk meets timing requirements for your target frequency. rst_n is asynchronous.

### Instantiation Example

Verification

The provided testbench validates:

Reset behavior (registers zeroed).
Byte-strobed writes to the data register.
IRQ triggering on pin state changes.
IRQ clearing via control register.

### Running Simulation

### Expected Log Output

TC1 PASS reset check
TC1 PASS irq zero after reset
TC2 PASS byte_strobe[0] write (and 1-3)
TC3 PASS irq set on gpio_in change
TC3 PASS irq sticky
TC3 PASS irq cleared
TC4 PASS data read back
Simulation ends with INFO: PASS.

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