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Interface Protocols

Lightweight I²C Slave Controller (Standard Mode)

A lightweight I²C slave controller that translates I²C read/write operations into simple register file transfers with clock stretching support.

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About this block

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Lightweight I²C Slave Controller (Standard Mode) is a SystemVerilog reference block in the Interface Protocols catalog. UART, SPI, I2C, and other serial or peripheral protocol interfaces. Marked Hard: a larger reference. Simulate the packaged testbench before you change the RTL.

This IP provides a minimal, resource-efficient I²C slave implementation for standard mode (100 kHz). It is designed for embedded systems requiring basic I²C connectivity with simple register file interfacing. The controller supports clock stretching, 7-bit address matching, and basic TX/RX data handling. It serves as a foundational block for more complex I²C peripherals or simple sensor interfaces.

This IP implements a lightweight I²C slave controller for standard mode operations. It translates I²C read/write operations into simple register file transfers. The design supports clock stretching and address matching. It is suitable for embedded systems requiring basic I²C connectivity.

  1. Choose Open in IDE. RTL Studio loads the packaged workspace for Lightweight I²C Slave Controller (Standard Mode).
  2. Read the SystemVerilog module in the editor. The catalog line for this block: A lightweight I²C slave controller that translates I²C read/write operations into simple register file transfers with clock stretching support.
  3. Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
  4. Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

  • Supports I²C standard mode (100 kHz).
  • Implements START and STOP condition detection.
  • Handles 7-bit address matching.
  • Provides TX and RX data interfaces with valid/ready handshaking.
  • Includes clock stretching capability.
  • Uses a simple, synthesizable state machine for control.

Architecture

The controller uses a finite state machine (FSM) to manage bus states. States include IDLE, ADDR_PHASE, DATA_READ, DATA_WRITE, and STOP_RESTART. Edge detection logic identifies START and STOP conditions on the SDA line. Shift registers capture address and data bits from the I²C bus. An address comparator validates incoming transactions against a target address. Data is shifted in or out based on the R/W bit direction.

Verification

The design includes a testbench for functional verification. Tests cover reset behavior, START condition, and STOP condition. Simulation results confirm correct state transitions. All test cases passed in the verification suite.

Test CaseDescriptionResult
TC1Basic Reset and Idle StatePASS
TC2START Condition DetectionPASS
TC3STOP Condition DetectionPASS

Limitations

  • Only supports standard mode speed (100 kHz).
  • Does not support general call or broadcast addresses.
  • No support for 10-bit addressing mode.
  • Limited to single-byte transactions per START/STOP pair.
  • No hardware flow control beyond basic ready/valid handshake.

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