RTL Studio Open IDE

Interface Protocols

Lightweight I²C Master Controller (Standard Mode)

A lightweight I²C master controller supporting Standard Mode (100 kHz) with configurable clock parameters and basic transaction control.

Open in IDE Category

About this block

Simulate it in the Verilog IDE

Hardverilogsimsyn

Lightweight I²C Master Controller (Standard Mode) is a Verilog reference block in the Interface Protocols catalog. UART, SPI, I2C, and other serial or peripheral protocol interfaces. Marked Hard: a larger reference. Simulate the packaged testbench before you change the RTL.

This IP provides a lightweight I²C master controller supporting Standard Mode (100 kHz). It implements a state-machine-based approach for generating I²C start, address, data, and ACK/NACK conditions. The design is parameterizable for system clock frequency and target I²C clock speed.

It supports both write and read transaction sequences with basic ACK monitoring. The controller is designed for easy integration into embedded systems requiring simple I²C communication without the overhead of a full I²C peripheral.

This lightweight I²C master controller is ideal for simple embedded systems requiring Standard Mode communication. It offers a straightforward interface for initiating transactions and monitoring status flags. The parameterizable clock division allows integration with various system clock frequencies. Integrators should ensure proper pull-up resistors are connected to the SDA and SCL lines for correct operation. For detailed internal implementation, refer to the source code comments.

  1. Choose Open in IDE. RTL Studio loads the packaged workspace for Lightweight I²C Master Controller (Standard Mode).
  2. Read the Verilog module in the editor. The catalog line for this block: A lightweight I²C master controller supporting Standard Mode (100 kHz) with configurable clock parameters and basic transaction control.
  3. Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
  4. Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

  • Standard Mode Support: Operates at 100 kHz I²C clock speed.
  • Parameterizable: Configurable system clock (CLK_FREQ) and I²C clock (I2C_FREQ) via Verilog parameters.
  • Protocol Handling: Automatically generates Start, Stop, Address, Data, and ACK/NACK conditions.
  • Simple Interface: Separate control interface for transaction initiation (start_req) and status reporting (transaction_done, ack_received).
  • Tri-State Management: Internally manages SDA tri-state buffers based on the I²C protocol state.
  • Synthesis Ready: Simple, clean Verilog implementation suitable for FPGA and ASIC synthesis.

Ports

Port NameDirectionWidthDescription
clkInput1System clock input
rst_nInput1Active-low asynchronous reset
start_reqInput1Request to start a new transaction. Must be asserted for at least one clock cycle.
slave_addrInput77-bit slave address
rw_bitInput10 for Write, 1 for Read
data_validInput1Valid data on tx_data for write operations. Asserted when data is ready.
tx_dataInput8Data byte to transmit during write operations.
rx_dataOutput8Data byte received during read operations. Valid when rx_valid is asserted.
rx_validOutput1Indicates that rx_data is valid. Asserted when a byte is successfully received.
ack_receivedOutput1Indicates if an ACK was received from the slave (0=ACK, 1=NACK).
transaction_doneOutput1Indicates transaction completion. Asserted when the transaction finishes.
sclOutput1I²C Serial Clock line

> Note on Read Operations: This lightweight controller supports single-byte read transactions. For multi-byte reads, the user must manage the transaction sequencing by re-asserting start_req after transaction_done is detected. The IP handles the internal tri-state switching for SDA automatically.

Architecture

The controller operates through a finite state machine that manages the I²C bus protocol. It handles clock stretching detection (basic) and generates the necessary waveforms.

Integration

### 1. Parameter Configuration Configure the clock frequencies in your instantiation or top-level module:

### 2. Hardware Requirements

  • Pull-up Resistors: I²C lines (SDA and SCL) must have external pull-up resistors (typically 4.7kΩ) connected to VCC. The controller outputs tri-state signals.
  • Clock Domain: Ensure clk is stable and meets setup/hold times for the control signals.

### 3. Transaction Flow

  1. Assert start_req along with slave_addr, rw_bit, and tx_data (if writing).
  2. Assert data_valid if tx_data contains valid data for a write operation.
  3. Wait for transaction_done to assert.
  4. Check ack_received to verify if the slave acknowledged the transaction.
  5. Deassert start_req to prepare for the next transaction.

#### Multi-Byte Transaction Example For multi-byte writes:

  1. Start transaction with first byte.
  2. Wait for transaction_done.
  3. If more bytes to send, assert start_req again with the same slave_addr and rw_bit, and provide the next tx_data and data_valid.

Verification

The design includes a testbench (tb_i2c_master_lite.v) that validates basic write and read transactions. Simulation is performed using Icarus Verilog.

### Test Results

  • TC1 (Write Transaction): PASS
  • TC2 (Read Transaction): PASS

### Simulation Setup

  1. Install Icarus Verilog.
  2. Run the simulation: iverilog -o sim tb_i2c_master_lite.v i2c_master_lite.v && vvp sim
  3. View the VCD waveform using a compatible viewer (e.g., GTKWave, RtlStudio).

More in Interface Protocols

All Interface Protocols blocks