Interface Protocols

SPI Slave Controller (Mode 0)

Synthesizable SPI slave with ready/valid byte interface, LSB-first Mode 0 shifting, and chip-select framed transfers.

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About this block

Simulate it in the Verilog IDE

Hardsystemverilogsimsyn

SPI Slave Controller (Mode 0) is a SystemVerilog reference block in the Interface Protocols catalog. UART, SPI, I2C, and other serial or peripheral protocol interfaces. Marked Hard: a larger reference. Simulate the packaged testbench before you change the RTL.

This OpenIP provides a synthesizable SPI slave with an internal ready/valid byte interface. The core shifts MOSI data LSB-first on rising SCK edges while driving MISO on falling edges. Verified with Verilator self-checking tests for single-byte and multi-byte transfers.

Choose Open in IDE. RTL Studio loads the packaged workspace for SPI Slave Controller (Mode 0).
Read the SystemVerilog module in the editor. The catalog line for this block: Synthesizable SPI slave with ready/valid byte interface, LSB-first Mode 0 shifting, and chip-select framed transfers.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

Parameterized data width (default 8 bits).
SHIFT_DIR parameter (LSB_FIRST default).
Combinatorial load acknowledge when idle.
RX valid held until bus_rdy_i handshake clears the beat.
Chip-select-gated frame handling.

Ports

Port	Direction	Width	Description
`clk_i`	input	1	System clock
`rst_ni`	input	1	Active-low reset
`sck_i`	input	1	SPI clock
`miso_o`	output	1	SPI MISO
`mosi_i`	input	1	SPI MOSI
`cs_ni`	input	1	Active-low chip select
`bus_req_i`	input	1	Load request (tie high when loading)
`bus_ack_o`	output	1	TX shadow register loaded
`tx_data_i`	input	DATA_WIDTH	TX payload for MISO
`tx_valid_i`	input	1	TX payload valid
`bus_data_o`	output	DATA_WIDTH	Received MOSI byte
`bus_valid_o`	output	1	Received byte valid

Parameters

Parameter	Default	Description
`DATA_WIDTH`	8	Bits per SPI frame
`SHIFT_DIR`	`"LSB_FIRST"`	Bit order on the wire

Integration

Pulse bus_rdy_i after reading bus_data_o to release bus_valid_o. Load tx_data_i with tx_valid_i and bus_rdy_i high while cs_ni is inactive. Keep sck_i low when idle for Mode 0 operation.

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