Interface Protocols

Synthesizable SystemVerilog UART Core (8-N-1)

A synthesizable 8-N-1 UART with valid/ready TX/RX handshakes and parameterizable baud timing.

Open in IDE Category

About this block

Simulate it in the Verilog IDE

Hardsystemverilogsimsyn

Synthesizable SystemVerilog UART Core (8-N-1) is a SystemVerilog reference block in the Interface Protocols catalog. UART, SPI, I2C, and other serial or peripheral protocol interfaces. Marked Hard: a larger reference. Simulate the packaged testbench before you change the RTL.

This OpenIP provides a compact 8-N-1 UART transmitter and receiver with valid/ready handshakes.

Baud timing is generated from fixed CLK_FREQ and BAUD_RATE parameters (default 100 MHz / 115200).

The design is fully synthesizable and verified with Verilator.

Choose Open in IDE. RTL Studio loads the packaged workspace for Synthesizable SystemVerilog UART Core (8-N-1).
Read the SystemVerilog module in the editor. The catalog line for this block: A synthesizable 8-N-1 UART with valid/ready TX/RX handshakes and parameterizable baud timing.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

Separate TX and RX finite-state machines.
Programmable baud via parameters (no runtime register programming).
tx_ready / tx_busy status for transmit flow control.
rx_valid / rx_ready receive handshake with stop-bit checking.
Self-checking testbench with seven directed test cases.

Ports

Port	Direction	Width	Description
`clk_i`	input	1	System clock
`rst_n_i`	input	1	Active-low reset
`tx_valid_i`	input	1	TX byte launch
`tx_data_i`	input	8	TX payload
`tx_ready_o`	output	1	TX accepts new byte
`tx_pin_o`	output	1	Serial TX line
`tx_busy_o`	output	1	TX serializer active
`rx_valid_o`	output	1	RX byte available
`rx_data_o`	output	8	RX payload
`rx_ready_i`	input	1	RX consumer ready
`rx_pin_i`	input	1	Serial RX line

Parameters

Parameter	Default	Description
`CLK_FREQ`	100_000_000	Clock frequency in Hz
`BAUD_RATE`	115200	UART line rate

Integration

Tie rx_pin_i high when idle. Hold rx_ready_i high unless software back-pressure is required. Adjust CLK_FREQ / BAUD_RATE to match your SoC clock before synthesis.

More in Interface Protocols

All Interface Protocols blocks