Interface Protocols

UART with Integrated TX/RX FIFOs

8N1 UART Core with Configurable Depth TX and RX FIFOs. Supports backpressure and interrupt-ready status flags.

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About this block

Simulate it in the Verilog IDE

Hardsystemverilogsimsyn

UART with Integrated TX/RX FIFOs is a SystemVerilog reference block in the Interface Protocols catalog. UART, SPI, I2C, and other serial or peripheral protocol interfaces. Marked Hard: a larger reference. Simulate the packaged testbench before you change the RTL.

This OpenIP provides a synthesizable 8-N-1 UART with separate TX and RX FIFOs. Host traffic uses ready/valid handshakes on each FIFO while serial I/O uses tx_pin_o and rx_pin_i. Verified with Verilator loopback tests.

Choose Open in IDE. RTL Studio loads the packaged workspace for UART with Integrated TX/RX FIFOs.
Read the SystemVerilog module in the editor. The catalog line for this block: 8N1 UART Core with Configurable Depth TX and RX FIFOs. Supports backpressure and interrupt-ready status flags.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

Parameterized DATA_WIDTH, FIFO_DEPTH, CLK_FREQ, and BAUD_RATE.
TX FIFO write interface: tx_din, tx_valid, tx_ready.
RX FIFO read interface: rx_dout, rx_valid, rx_ready.
Status flags: tx_empty, tx_full, rx_empty, rx_full.
Interrupt-style flags: tx_int, rx_int (FIFO non-empty indicators).

Ports

Port	Direction	Width	Description
`clk`	input	1	System clock
`rst_n`	input	1	Active-low reset
`tx_din`	input	DATA_WIDTH	TX FIFO write data
`tx_valid`	input	1	TX FIFO write valid
`tx_ready`	output	1	TX FIFO not full
`rx_dout`	output	DATA_WIDTH	RX FIFO read data
`rx_valid`	output	1	RX FIFO not empty
`rx_ready`	input	1	RX FIFO read enable
`tx_pin_o`	output	1	Serial TX pin
`rx_pin_i`	input	1	Serial RX pin
`tx_empty`	output	1	TX FIFO empty
`tx_full`	output	1	TX FIFO full

Parameters

Parameter	Default	Description
`DATA_WIDTH`	8	Byte width
`FIFO_DEPTH`	16	Entries per FIFO
`BAUD_RATE`	115200	Line rate in Hz
`CLK_FREQ`	50_000_000	Clock frequency in Hz

Integration

Tie rx_pin_i high when idle. Use tx_valid/tx_ready to push bytes and rx_valid/rx_ready to pop received bytes. For loopback wiring, connect rx_pin_i to tx_pin_o through your board or testbench. Allow one idle frame between back-to-back host sessions if the RX engine was previously active.

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