Arithmetic & Math

Absolute Difference 8-Bit — L1 Upgrade — L2 Upgrade

Glitch-free 8-bit absolute difference calculator with sticky saturation flag and registered outputs.

Open in IDE Category Wiki · arithmetic

About this block

Simulate it in the Verilog IDE

Mediumverilogsimsyn

Absolute Difference 8-Bit — L1 Upgrade — L2 Upgrade is a Verilog reference block in the Arithmetic & Math catalog. Adders, multipliers, dividers, ALUs, and arithmetic datapaths. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This IP implements a glitch-free, registered absolute difference calculator for 8-bit operands. It is designed for high-frequency digital systems where stable, registered outputs are required to prevent timing hazards in downstream logic.

Key Capabilities:

Computes $|A - B|$ for two 8-bit inputs.
Provides a sticky saturation flag (sat_flag) that asserts when inputs are equal ($A=B$) or the difference is maximal ($|A-B|=255$).
Supports asynchronous clearing of the saturation flag via clear_sat.
Fully registered outputs ensure timing closure and glitch-free operation.

Choose Open in IDE. RTL Studio loads the packaged workspace for Absolute Difference 8-Bit — L1 Upgrade — L2 Upgrade.
Read the Verilog module in the editor. The catalog line for this block: Glitch-free 8-bit absolute difference calculator with sticky saturation flag and registered outputs.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

Glitch-Free Operation: All outputs (diff, sat_flag) are registered on the rising edge of clk, ensuring stable data for downstream logic.
Sticky Saturation Flag: The sat_flag remains asserted once triggered until explicitly cleared. It indicates:

- Equality: $A = B$ - Maximum Difference: $|A - B| = 255$ (i.e., $0x00$ vs $0xFF$)

Asynchronous Clear: Dedicated clear_sat signal allows immediate reset of the saturation flag, independent of the clock edge (subject to reset synchronization if required by downstream logic).
Active-Low Reset: Global reset (rst_n) clears all internal states and outputs to zero.
Enable Control: Data capture is gated by an en signal, allowing for clock gating or pipeline control.

Ports

Port Name	Direction	Width	Description
`clk`	Input	1	Clock input (rising edge triggered)
`rst_n`	Input	1	Active-low asynchronous reset
`clear_sat`	Input	1	Asynchronous clear for saturation flag
`en`	Input	1	Enable signal for data capture
`a`	Input	8	First operand
`b`	Input	8	Second operand
`diff`	Output	8	Absolute difference result ($	A - B	$)
`sat_flag`	Output	1	Sticky saturation indicator

Verification

The provided testbench (tb/tb_absdiff_glitch_free_8bit_sticky_sat_flag.v) verifies the following scenarios:

TC1: Correct difference when $A > B$.
TC2: Correct difference when $B > A$.
TC3: Saturation flag can be cleared asynchronously.
TC4: Saturation flag sets on maximum difference ($255$).
TC5: Saturation flag clears correctly after assertion.
TC6: Global reset clears all outputs.

### Running Simulation

Open your preferred HDL simulator (e.g., ModelSim, VCS, Xcelium).
Compile the RTL file: rtl/absdiff_glitch_free_8bit_sticky_sat_flag.v.
Compile the testbench: tb/tb_absdiff_glitch_free_8bit_sticky_sat_flag.v.
Run the simulation.
Check the log for:

- TC1 PASS through TC6 PASS - INFO: PASS

Constraints

Max Frequency: Dependent on the target technology library and routing. The registered outputs ensure that the critical path is limited to the combinational logic between registers.
Reset Synchronization: If clear_sat is used in a synchronous domain, it is recommended to synchronize it with the clock domain to avoid metastability.

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