Arithmetic & Math

8-Bit Absolute Value — L1 Upgrade

Registered 8-bit absolute value calculator with sticky overflow detection for -128.

Open in IDE Category Wiki · arithmetic

About this block

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8-Bit Absolute Value — L1 Upgrade is a Verilog reference block in the Arithmetic & Math catalog. Adders, multipliers, dividers, ALUs, and arithmetic datapaths. Marked Easy: a small block you can read, simulate, and synthesize in one sitting.

This IP core implements a registered 8-bit absolute value calculator for two's complement signed integers.

It features a sticky overflow flag that detects the unique edge case of input -128 (0x80), which cannot be represented as a positive 8-bit signed integer.

Once triggered, the overflow flag remains set until reset, ensuring system-level awareness of this arithmetic limitation.

Positive Inputs: Passed through unchanged.
Negative Inputs: Converted to positive using two's complement inversion.
Overflow Handling: The input -128 triggers the ovf_sticky flag. This flag is asynchronous-resettable but otherwise latches high permanently during operation to indicate that an overflow event has occurred.

Choose Open in IDE. RTL Studio loads the packaged workspace for 8-Bit Absolute Value — L1 Upgrade.
Read the Verilog module in the editor. The catalog line for this block: Registered 8-bit absolute value calculator with sticky overflow detection for -128.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Ports

Port Name	Direction	Width	Description
`clk`	Input	1	Clock input (positive edge triggered)
`rst_n`	Input	1	Active-low asynchronous reset
`en`	Input	1	Synchronous enable signal
`din`	Input	8	Signed 8-bit input data
`dout`	Output	8	Absolute value output
`ovf_sticky`	Output	1	Sticky overflow flag (latches high on -128)

Architecture

The design consists of a registered datapath with combinational overflow detection logic.

Combinational Detection: Checks if din == 8'h80 (-128).
Registered Datapath: On the positive clock edge, if en is high:

- Computes absolute value: ~din + 1 if negative, else din. - Updates dout. - Updates ovf_sticky: If overflow was detected, the flag is set to 1. It never clears unless rst_n is asserted.

Verification

The provided testbench (tb/tb_absolute_value_registered_sticky_8bit.v) validates six scenarios:

Test Case	Input	Expected `dout`	Expected `ovf_sticky`	Description
TC1	5	5	0	Positive input
TC2	-5	5	0	Negative input
TC3	-128	128	1	Overflow edge case
TC4	10	10	1	Subsequent input after overflow
TC5	0	0	1	Zero after overflow
TC6	Hold	Hold	Hold	Disabled state

Run the simulation to verify these results. The log should report PASS for all test cases.

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