Arithmetic & Math

1-Bit Full Adder

A combinational 1-bit full adder that computes sum and carry-out from three input bits.

Open in IDE Category Wiki · arithmetic

About this block

Simulate it in the Verilog IDE

Easyverilogsimsyn

1-Bit Full Adder is a Verilog reference block in the Arithmetic & Math catalog. Adders, multipliers, dividers, ALUs, and arithmetic datapaths. Marked Easy: a small block you can read, simulate, and synthesize in one sitting.

This IP implements a combinational 1-bit full adder. It computes the sum and carry-out for three single-bit inputs (a, b, cin). The design uses standard XOR and AND-OR logic gates and is fully verified against the truth table.

This IP provides a verified, combinational 1-bit full adder core suitable for building multi-bit arithmetic units. It has no clock dependency and is ready for integration into larger datapaths.

Choose Open in IDE. RTL Studio loads the packaged workspace for 1-Bit Full Adder.
Read the Verilog module in the editor. The catalog line for this block: A combinational 1-bit full adder that computes sum and carry-out from three input bits.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Architecture

The module accepts three input bits: a, b, and cin. It produces two output bits: sum and cout.

Sum: Calculated as the XOR of all three inputs (a ^ b ^ cin).
Carry-out: Generated if any two inputs are high ((a & b) | (cin & (a ^ b))).

Ports

Port	Direction	Width	Description
a	Input	1	First operand bit
b	Input	1	Second operand bit
cin	Input	1	Carry-in bit
sum	Output	1	Sum result bit
cout	Output	1	Carry-out bit

Verification

The testbench covers all eight possible input combinations. It checks the sum and carry-out against expected truth table values. All eight test cases passed successfully.

Test Case	a	b	cin	Expected Sum	Expected Cout	Result
TC1	0	0	0	0	0	PASS
TC2	0	0	1	1	0	PASS
TC3	0	1	0	1	0	PASS
TC4	0	1	1	0	1	PASS
TC5	1	0	0	1	0	PASS
TC6	1	0	1	0	1	PASS
TC7	1	1	0	0	1	PASS
TC8	1	1	1	1	1	PASS

To run the simulation:

Open the project in your EDA tool.
Run the testbench tb_full_adder_1bit.v.
Check the Log panel for INFO: PASS.

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