Arithmetic & Math

1-Bit Full Adder — L1 Upgrade — L2 Upgrade

1-Bit Full Adder with saturation clamping and sticky signed overflow flag.

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About this block

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1-Bit Full Adder — L1 Upgrade — L2 Upgrade is a Verilog reference block in the Arithmetic & Math catalog. Adders, multipliers, dividers, ALUs, and arithmetic datapaths. Marked Easy: a small block you can read, simulate, and synthesize in one sitting.

This IP implements a 1-bit full adder with saturation arithmetic and sticky overflow detection. It is designed for low-bit-width arithmetic units where overflow handling and error tracking are critical.

Signed Interpretation:

Input 0 represents value 0.
Input 1 represents value -1.
The output sum is clamped to the valid 1-bit signed range [-1, 0] (represented as 1 and 0 respectively) when saturation occurs.

Sticky Overflow: A sticky flag (ovf_sticky) latches signed overflow events until explicitly cleared via the clr_sticky signal. This allows for error detection across multiple cycles without losing historical overflow information.

Choose Open in IDE. RTL Studio loads the packaged workspace for 1-Bit Full Adder — L1 Upgrade — L2 Upgrade.
Read the Verilog module in the editor. The catalog line for this block: 1-Bit Full Adder with saturation clamping and sticky signed overflow flag.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

Combinational Logic: Fast 1-bit sum and carry generation.
Saturation: Clamps the sum output to 1 (representing -1, the minimum value) on carry-out or saturation conditions.
Sticky Overflow Flag: Registers signed overflow events and holds them until cleared.
Control Signals: Synchronous reset (rst_n) and asynchronous clear (clr_sticky) for the sticky flag.
Verified: Functionally verified with Icarus Verilog simulation.

Ports

Port Name	Direction	Width	Description
`clk`	Input	1	Clock input
`rst_n`	Input	1	Active-low synchronous reset
`clr_sticky`	Input	1	Active-high clear for sticky overflow flag
`a`	Input	1	Operand A (0=0, 1=-1)
`b`	Input	1	Operand B (0=0, 1=-1)
`cin`	Input	1	Carry-in
`sum`	Output	1	Saturated sum result
`sat`	Output	1	Saturation flag (asserted on saturation)
`ovf_sticky`	Output	1	Sticky overflow flag

Architecture

The design consists of a raw adder core and control logic for saturation and overflow tracking.

Raw Adder: Computes the standard XOR sum and AND-OR carry.
Saturation Logic: Forces the sum to 1 if a carry-out occurs, ensuring the result stays within the 1-bit signed range.
Signed Overflow Detection: Detects overflow when two negative inputs (1) produce a positive sum (0) without carry, or two positive inputs (0) produce a negative sum (1) with carry.
Sticky Latch: Registers the overflow event. The flag remains set until clr_sticky is asserted or rst_n is de-asserted.

Verification

The testbench verifies basic addition, saturation clamping, and sticky flag behavior.

### Test Cases

Test Case	Inputs (a, b, cin)	Expected Sum	Expected Sat	Expected Ovf Sticky	Result
TC1	0, 0, 0	0	0	0	PASS
TC2	1, 0, 0	1	0	0	PASS
TC3	0, 1, 0	1	0	0	PASS
TC4	1, 1, 0	1	1	1	PASS
TC5	1, 1, 1	1	1	1	PASS
TC6	Clear Sticky	N/A	N/A	0	PASS
TC7	Set Sticky	N/A	N/A	1	PASS

### Running Simulation

To run the simulation:

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