Arithmetic & Math

4-bit Adder-Subtractor with Overflow

A 4-bit arithmetic unit supporting addition and subtraction with signed overflow detection using two's complement logic.

Open in IDE Category Wiki · arithmetic

About this block

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4-bit Adder-Subtractor with Overflow is a Verilog reference block in the Arithmetic & Math catalog. Adders, multipliers, dividers, ALUs, and arithmetic datapaths. Marked Easy: a small block you can read, simulate, and synthesize in one sitting.

This IP implements a 4-bit arithmetic unit capable of both addition and subtraction using two's complement logic. It features a ripple-carry architecture with explicit overflow detection for signed arithmetic. The module is designed for low-complexity applications where simplicity and predictability are prioritized over speed.

Choose Open in IDE. RTL Studio loads the packaged workspace for 4-bit Adder-Subtractor with Overflow.
Read the Verilog module in the editor. The catalog line for this block: A 4-bit arithmetic unit supporting addition and subtraction with signed overflow detection using two's complement logic.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

4-bit Operation: Handles operands a and b within the range [-8, 7] for signed arithmetic.
Dual Mode: Supports addition (sub=0) and subtraction (sub=1).
Signed Overflow Detection: Flags when the result exceeds the 4-bit signed range.
Carry Out: Provides the unsigned carry-out bit for chaining or unsigned arithmetic checks.
Self-Checking Testbench: Includes a comprehensive testbench (tb_adder_subtractor.v) verifying boundary conditions and overflow scenarios.

Architecture

The design uses a conditional XOR gate array to invert the subtrahend b when sub is high. The carry-in for the least significant bit is set to sub to complete the two's complement negation. Overflow is detected by XORing the carry into the most significant bit (MSB) with the carry out of the MSB.

Ports

Port Name	Direction	Width	Description
`a`	Input	[3:0]	First operand (minuend or augend)
`b`	Input	[3:0]	Second operand (subtrahend or addend)
`sub`	Input	1	Operation select: 0 for Add, 1 for Subtract
`sum`	Output	[3:0]	Result of the arithmetic operation
`cout`	Output	1	Carry out from the most significant bit
`overflow`	Output	1	Signed overflow flag

Verification

The testbench tb_adder_subtractor.v covers:

Basic addition and subtraction.
Boundary conditions (e.g., 0, max positive, min negative).
Overflow scenarios for both addition and subtraction.

Test Case	Description	Expected Result	Status
TC1.1	0 + 0	sum=0, cout=0, ovf=0	PASS
TC1.2	1 + 1	sum=2, cout=0, ovf=0	PASS
TC1.3	7 + 1 (Overflow)	sum=8, cout=0, ovf=1	PASS
TC1.5	-8 + -1 (Overflow)	sum=7, cout=1, ovf=1	PASS
TC2.1	0 - 0	sum=0, cout=1, ovf=0	PASS
TC2.2	5 - 3	sum=2, cout=1, ovf=0	PASS
TC2.3	5 - 7	sum=-2, cout=0, ovf=0	PASS
TC2.4	5 - (-8) (Overflow)	sum=-3, cout=0, ovf=1	PASS
TC2.5	-8 - 1 (Overflow)	sum=7, cout=1, ovf=1	PASS

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