Arithmetic & Math

16-Bit Signed Adder with Overflow

A synchronous 16-bit two's complement signed adder with overflow detection logic.

Open in IDE Category Wiki · arithmetic

About this block

Simulate it in the Verilog IDE

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16-Bit Signed Adder with Overflow is a Verilog reference block in the Arithmetic & Math catalog. Adders, multipliers, dividers, ALUs, and arithmetic datapaths. Marked Easy: a small block you can read, simulate, and synthesize in one sitting.

This 16-bit signed adder provides reliable arithmetic with explicit overflow detection for safety-critical applications.

The synchronous interface allows easy integration into pipelined data paths.

Comprehensive test coverage ensures robust handling of edge cases and boundary conditions.

Choose Open in IDE. RTL Studio loads the packaged workspace for 16-Bit Signed Adder with Overflow.
Read the Verilog module in the editor. The catalog line for this block: A synchronous 16-bit two's complement signed adder with overflow detection logic.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Architecture

The design uses a 17-bit internal wire to capture the full carry-out for accurate overflow calculation. Overflow logic checks if the carry into the MSB differs from the carry out of the MSB. The result is registered to ensure synchronous operation and timing closure.

Ports

Port Name	Direction	Width	Description
`clk`	Input	1	Clock input for sequential logic
`rst_n`	Input	1	Active-low asynchronous reset
`a`	Input	16	First 16-bit signed operand
`b`	Input	16	Second 16-bit signed operand
`load`	Input	1	Load enable signal
`sum`	Output	16	16-bit signed sum result
`overflow`	Output	1	Overflow flag (1 if overflow occurred)

Verification

The testbench covers five key scenarios to ensure correctness:

Basic positive addition: Verifies standard arithmetic behavior.
Basic negative addition: Verifies two's complement handling for negative numbers.
Positive overflow: Checks the boundary condition of adding the maximum positive value.
Negative overflow: Checks the boundary condition of adding the minimum negative value.
Mixed sign addition: Confirms that overflow never occurs when signs differ.

Test Case	Description	Expected Sum	Expected Overflow	Status
TC1	Positive Addition (10 + 20)	30	0	PASS
TC2	Negative Addition (-10 + -20)	-30	0	PASS
TC3	Positive Overflow (Max + 1)	-32768	1	PASS
TC4	Negative Overflow (Min - 1)	32767	1	PASS
TC5	Mixed Signs (10 + -10)	0	0	PASS

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