Arithmetic & Math

2-Bit Saturating Up/Down Counter — L2 Upgrade

A 2-bit saturating up/down counter with Gray code output and parallel load capability.

Open in IDE Category Wiki · arithmetic

About this block

Simulate it in the Verilog IDE

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2-Bit Saturating Up/Down Counter — L2 Upgrade is a Verilog reference block in the Arithmetic & Math catalog. Adders, multipliers, dividers, ALUs, and arithmetic datapaths. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This IP core implements a 2-bit saturating up/down counter with Gray code output.

It is designed for educational purposes (Level 2 difficulty) and simple state machine applications where glitch-free transitions are preferred.

The counter uses binary internal state for arithmetic efficiency and converts to Gray code for the output port.

Choose Open in IDE. RTL Studio loads the packaged workspace for 2-Bit Saturating Up/Down Counter — L2 Upgrade.
Read the Verilog module in the editor. The catalog line for this block: A 2-bit saturating up/down counter with Gray code output and parallel load capability.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

2-Bit Counting: Counts from 0 to 3.
Gray Code Output: Output sequence is 00, 01, 11, 10 to minimize switching noise.
Saturating Logic: Clamps at maximum (3) when counting up and minimum (0) when counting down.
Parallel Load: Allows immediate setting of the counter value via load_val.
Direction Control: Supports both up and down counting modes.
Interrupt Request: Asserts irq when the counter reaches the maximum value (3).

Ports

Port Name	Direction	Width	Description
`clk`	Input	1	Clock input
`rst_n`	Input	1	Active-low reset
`load`	Input	1	Parallel load enable
`up_down`	Input	1	Count direction (1=Up, 0=Down)
`load_val`	Input	2	Value to load into counter
`enable`	Input	1	Count enable
`q_gray`	Output	2	Gray code count output
`irq`	Output	1	Interrupt request at max count

Verification

The testbench (tb/tb_saturating_counter_gray_load_2bit.v) covers the following scenarios:

Test Case	Description	Result
TC1	Reset to 0 (Gray 00)	PASS
TC2	Up count saturation (0->3)	PASS
TC3	Down count saturation (3->0)	PASS
TC4	Parallel load functionality	PASS
TC5	IRQ assertion at max count	PASS
TC6	IRQ deassertion at non-max	PASS

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