Arithmetic & Math

32-Bit Equality Comparator — L1 Upgrade — L2 Upgrade

Registered 32-bit equality comparator with sticky saturation flag for underflow detection.

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32-Bit Equality Comparator — L1 Upgrade — L2 Upgrade is a Verilog reference block in the Arithmetic & Math catalog. Adders, multipliers, dividers, ALUs, and arithmetic datapaths. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This IP implements a registered 32-bit equality comparator with a sticky saturation flag.

It compares two 32-bit operands (a and b) and asserts an output when they are equal.

Additionally, it detects underflow conditions (where a < b) and sets a sticky saturation flag that persists until explicitly cleared via the clear_sat signal.

Choose Open in IDE. RTL Studio loads the packaged workspace for 32-Bit Equality Comparator — L1 Upgrade — L2 Upgrade.
Read the Verilog module in the editor. The catalog line for this block: Registered 32-bit equality comparator with sticky saturation flag for underflow detection.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Architecture

The module registers input operands a and b on the rising clock edge when valid_in is asserted. Equality is determined by comparing the registered values. A saturation flag is set if a is less than b during the comparison cycle. The saturation flag remains high until the clear_sat signal is asserted, provided valid_in is also high.

Ports

Port Name	Direction	Width	Description
`clk`	Input	1	Clock input
`rst_n`	Input	1	Active-low reset
`clear_sat`	Input	1	Clear saturation flag
`valid_in`	Input	1	Valid input enable
`a`	Input	32	Operand A
`b`	Input	32	Operand B
`eq_out`	Output	1	Equality output
`sat_flag`	Output	1	Sticky saturation flag

Verification

The testbench verifies six key scenarios to ensure functional correctness:

TC1: Basic Equality detection for identical operands.
TC2: Basic Inequality detection for distinct operands.
TC3: Saturation flag setting on underflow (a < b).
TC4: Sticky nature of the saturation flag (persists across cycles).
TC5: Clearing of the saturation flag via clear_sat.
TC6: Reset behavior of all outputs.

Test Case	Description	Expected Result
TC1	Basic Equality	`eq_out` = 1, `sat_flag` = 0
TC2	Basic Inequality	`eq_out` = 0, `sat_flag` = 0
TC3	Underflow Saturation	`eq_out` = 0, `sat_flag` = 1
TC4	Sticky Saturation	`eq_out` = 0, `sat_flag` = 1
TC5	Clear Saturation	`eq_out` = 0, `sat_flag` = 0
TC6	Reset Behavior	`eq_out` = 0, `sat_flag` = 0

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