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Arithmetic & Math

4-Input 8-Bit Adder Tree — L2 Upgrade

4-input 8-bit adder tree with saturating arithmetic and sticky overflow flag.

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About this block

Simulate it in the Verilog IDE

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4-Input 8-Bit Adder Tree — L2 Upgrade is a Verilog reference block in the Arithmetic & Math catalog. Adders, multipliers, dividers, ALUs, and arithmetic datapaths. Marked Easy: a small block you can read, simulate, and synthesize in one sitting.

This IP core implements a 4-input 8-bit unsigned adder tree with saturating arithmetic and a sticky saturation flag. It is designed for fixed-point accumulation applications where overflow detection is critical.

The module computes the sum of four 8-bit inputs, saturating the result to 255 (8'hFF) if the true sum exceeds the 8-bit range. A sticky sat flag remains asserted until explicitly cleared via the clr_sat signal.

  1. Choose Open in IDE. RTL Studio loads the packaged workspace for 4-Input 8-Bit Adder Tree — L2 Upgrade.
  2. Read the Verilog module in the editor. The catalog line for this block: 4-input 8-bit adder tree with saturating arithmetic and sticky overflow flag.
  3. Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
  4. Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

  • 4-Input Addition: Supports four parallel 8-bit operands.
  • Saturating Arithmetic: Output clamps to 255 (8'hFF) on overflow.
  • Sticky Saturation Flag: sat output remains high after any overflow event until cleared.
  • Reset Control: Asynchronous active-low reset (rst_n) clears all state. Synchronous clear (clr_sat) resets only the saturation flag.
  • Registered Outputs: Registered sum and sat outputs ensure stable timing for downstream logic.

Ports

Port NameDirectionWidthDescription
clkInput1Clock input
rst_nInput1Asynchronous active-low reset
clr_satInput1Synchronous saturation flag clear
aInput8First 8-bit operand
bInput8Second 8-bit operand
cInput8Third 8-bit operand
dInput8Fourth 8-bit operand
sumOutput8Saturated sum result
satOutput1Sticky saturation flag

Integration

### Instantiation

Include the RTL file rtl/adder_tree_4x8_sticky_sat_flag.v in your project. Instantiate the module as follows:

### Usage Example

  1. Assert rst_n low to initialize the module.
  2. Deassert rst_n to begin operation.
  3. Provide 8-bit values to inputs a, b, c, and d.
  4. Monitor sum for the result. If sum is 255 and sat is 1, an overflow occurred.
  5. To clear the sticky flag, assert clr_sat high for one clock cycle.

Verification

The provided testbench (tb/tb_adder_tree_4x8_sticky_sat_flag.v) validates:

  • Normal addition without overflow.
  • Saturation behavior when sum > 255.
  • Sticky flag persistence across cycles.
  • Synchronous clear of the saturation flag.
  • Asynchronous reset functionality.

### Running Simulation

  1. Ensure your simulator supports SystemVerilog/Verilog.
  2. Run the simulation script provided in the sim/ directory (e.g., run_sim.sh or equivalent).
  3. Check the log output for INFO: PASS messages.

### Expected Results

The simulation log should contain:

  • TC1 PASS sum=40 sat=0
  • TC2 PASS sum=255 sat=1
  • TC3 PASS sum=4 sat=1
  • TC4 PASS sat=0
  • TC5 PASS sum=0 sat=0
  • TC6 PASS sum=255 sat=1
  • TC7 PASS sum=1 sat=1
  • INFO: PASS

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