Arithmetic & Math

8-Bit Carry-Save Adder (3:2) — L2 Upgrade

8-bit carry-save adder with signed saturation clamping and sticky saturation flag.

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8-Bit Carry-Save Adder (3:2) — L2 Upgrade is a Verilog reference block in the Arithmetic & Math catalog. Adders, multipliers, dividers, ALUs, and arithmetic datapaths. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This IP core implements an 8-bit Carry-Save Adder with signed saturation clamping and a sticky saturation flag. It is designed for Level 2 complexity in arithmetic datapath applications.

The module performs a 3:2 reduction to compute the sum of two 8-bit signed operands. It detects signed overflow and unsigned carry-out to trigger saturation logic. When saturation occurs, the output is clamped to the minimum (-128) or maximum (127) representable value. A sticky sat_flag persists until explicitly cleared by the clear_sat signal. Outputs are registered to ensure timing closure and valid handshake protocols.

This IP implements an 8-bit Carry-Save Adder with signed saturation clamping and a sticky saturation flag. It is designed for Level 2 complexity in arithmetic datapath applications. The module performs a 3:2 reduction to compute the sum of two 8-bit signed operands. It detects signed overflow and unsigned carry-out to trigger saturation logic. When saturation occurs, the output is clamped to the minimum (-128) or maximum (127) representable value. A sticky sat_flag persists until explicitly cleared by the clear_sat signal. Outputs are registered to ensure timing closure and valid handshake protocols.

Choose Open in IDE. RTL Studio loads the packaged workspace for 8-Bit Carry-Save Adder (3:2) — L2 Upgrade.
Read the Verilog module in the editor. The catalog line for this block: 8-bit carry-save adder with signed saturation clamping and sticky saturation flag.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

8-bit Signed Addition: Uses carry-save technique for improved timing.
Saturation Clamping: Clamps results to the signed 8-bit range [-128, 127].
Sticky Saturation Flag: sat_flag remains high until cleared by clear_sat.
Registered Outputs: Ensures timing closure and valid handshake protocols.
Verification: Includes a comprehensive testbench with 7 verification cases.

Ports

Port	Direction	Width	Description
`clk`	Input	1	Clock input
`rst_n`	Input	1	Active-low reset
`clear_sat`	Input	1	Synchronous clear for saturation flag
`valid_in`	Input	1	Input valid handshake
`a`	Input	[7:0]	First 8-bit signed operand
`b`	Input	[7:0]	Second 8-bit signed operand
`valid_out`	Output	1	Output valid handshake
`sum`	Output	[7:0]	Clamped 8-bit signed sum
`sat_flag`	Output	1	Sticky saturation flag

Verification

The testbench validates basic addition, saturation overflow, saturation underflow, sticky flag persistence, flag clearing, zero addition, and mixed sign addition.

Test Case	Description	Expected Result
TC1	Basic Positive Addition (10 + 20)	sum=30, sat=0
TC2	Signed Overflow (100 + 50)	sum=127, sat=1
TC3	Signed Underflow (-100 + -50)	sum=-128, sat=1
TC4	Sticky Flag Persistence	sat=1 after normal add
TC5	Clear Saturation Flag	sat=0 after clear_sat
TC6	Zero Addition (0 + 0)	sum=0, sat=0
TC7	Negative + Positive (-10 + 10)	sum=0, sat=0

All 7 test cases passed in the simulation log.

### Expected Simulation Output

After running the simulation, the Log panel should show:

TC1 PASS: 10 + 20 = 30
TC2 PASS: 100 + 50 = 127 (Clamped), Sat=1
TC3 PASS: -100 + -50 = -128 (Clamped), Sat=1
TC4 PASS: Sat flag remains sticky after normal add
TC5 PASS: Sat flag cleared
TC6 PASS: 0 + 0 = 0
TC7 PASS: -10 + 10 = 0
Simulation ends with INFO: PASS.

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