Arithmetic & Math

16-Bit Carry-Select Adder

A 16-bit carry-select adder that splits addition into two 8-bit blocks to reduce propagation delay.

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About this block

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16-Bit Carry-Select Adder is a Verilog reference block in the Arithmetic & Math catalog. Adders, multipliers, dividers, ALUs, and arithmetic datapaths. Marked Easy: a small block you can read, simulate, and synthesize in one sitting.

This IP implements a high-performance 16-bit carry-select adder in Verilog. By splitting the addition into two 8-bit blocks, it reduces propagation delay compared to a standard ripple-carry adder. Block 0 processes bits [7:0] using the actual carry-in, while Block 1 pre-computes sums for both possible carry-in values (0 and 1). Multiplexers then select the correct Block 1 result based on Block 0's carry-out.

This architecture offers an optimal balance between speed and hardware area, making it suitable for designs requiring moderate arithmetic performance.

This 16-bit carry-select adder provides efficient arithmetic operations. It is suitable for designs requiring moderate speed and low area. The implementation is fully verified with Icarus Verilog.

Choose Open in IDE. RTL Studio loads the packaged workspace for 16-Bit Carry-Select Adder.
Read the Verilog module in the editor. The catalog line for this block: A 16-bit carry-select adder that splits addition into two 8-bit blocks to reduce propagation delay.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

16-bit Unsigned Addition: Supports operands a and b of width 16 bits.
Carry Handling: Includes cin (carry-in) and cout (carry-out) ports.
Optimized Performance: Uses a two-level carry-select structure to minimize critical path delay.
Verified: Includes a comprehensive testbench with 8 test cases covering edge cases, overflow, and random values.

Ports

Port	Direction	Width	Description
`a`	Input	[15:0]	First operand
`b`	Input	[15:0]	Second operand
`cin`	Input	1	Carry-in
`sum`	Output	[15:0]	Sum result
`cout`	Output	1	Carry-out

Architecture

The adder is divided into two 8-bit blocks:

Block 0 (Bits [7:0]): Computes sum and carry-out using the actual cin.
Block 1 (Bits [15:8]): Pre-computes two potential sums and carry-outs:

- One assuming cin = 0. - One assuming cin = 1.

Selection: Multiplexers select the correct Block 1 result based on cout from Block 0.

Verification

The testbench covers zero addition, carry-in scenarios, and overflow cases. All eight test cases passed successfully during simulation.

Test Case	Description	Expected Result	Status
TC1	Zero addition	sum=0, cout=0	PASS
TC2	Zero addition with cin	sum=1, cout=0	PASS
TC3	Simple addition	sum=8, cout=0	PASS
TC4	Carry within block 0	sum=16, cout=0	PASS
TC5	Carry into block 1	sum=256, cout=0	PASS
TC6	Full overflow	sum=0, cout=1	PASS
TC7	Block boundary with cin	sum=257, cout=0	PASS
TC8	Random large values	sum=0x10245, cout=1	PASS

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