Arithmetic & Math

1-Bit Half Adder

A basic 1-bit half adder module that computes sum and carry from two input bits.

Open in IDE Category Wiki · arithmetic

About this block

Simulate it in the Verilog IDE

Easyverilogsimsyn

1-Bit Half Adder is a Verilog reference block in the Arithmetic & Math catalog. Adders, multipliers, dividers, ALUs, and arithmetic datapaths. Marked Easy: a small block you can read, simulate, and synthesize in one sitting.

This OpenIP provides a synthesizable, 1-bit half adder implemented in Verilog. It computes the sum and carry outputs for two single-bit inputs using standard XOR and AND logic. The design is fully verified with a comprehensive testbench covering all four input combinations.

Choose Open in IDE. RTL Studio loads the packaged workspace for 1-Bit Half Adder.
Read the Verilog module in the editor. The catalog line for this block: A basic 1-bit half adder module that computes sum and carry from two input bits.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Architecture

The half adder consists of two primary logic functions:

Sum: Exclusive OR (XOR) of inputs a and b.
Carry: Logical AND of inputs a and b.

Ports

Port Name	Direction	Width	Description
a	Input	1	First operand bit
b	Input	1	Second operand bit
sum	Output	1	Sum result (a XOR b)
carry	Output	1	Carry result (a AND b)

Verification

The testbench (tb/tb_half_adder_1bit.v) verifies all four possible input combinations using the Icarus Verilog engine.

### Running Simulation

### Expected Results

The simulation log should display:

INFO: TC1 PASS (0+0)
INFO: TC2 PASS (0+1)
INFO: TC3 PASS (1+0)
INFO: TC4 PASS (1+1)
INFO: PASS

Test Case	Input a	Input b	Expected Sum	Expected Carry	Result
TC1	0	0	0	0	PASS
TC2	0	1	1	0	PASS
TC3	1	0	1	0	PASS
TC4	1	1	0	1	PASS

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