Arithmetic & Math

4-Digit BCD Adder with Carry Propagation — L2 Upgrade

A synchronous 4-digit BCD adder with carry propagation and a sticky saturation flag for overflow detection.

Open in IDE Category Wiki · arithmetic

About this block

Simulate it in the Verilog IDE

Mediumsystemverilogsimsyn

4-Digit BCD Adder with Carry Propagation — L2 Upgrade is a SystemVerilog reference block in the Arithmetic & Math catalog. Adders, multipliers, dividers, ALUs, and arithmetic datapaths. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This IP implements a synchronous 4-digit Binary-Coded Decimal (BCD) adder.

It supports carry propagation between decimal digits and includes a sticky saturation flag for overflow detection.

The design is suitable for digital signal processing applications where decimal arithmetic is required.

Choose Open in IDE. RTL Studio loads the packaged workspace for 4-Digit BCD Adder with Carry Propagation — L2 Upgrade.
Read the SystemVerilog module in the editor. The catalog line for this block: A synchronous 4-digit BCD adder with carry propagation and a sticky saturation flag for overflow detection.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

4-Digit BCD Addition: Adds two 16-bit BCD inputs to produce a 16-bit BCD sum.
Carry Propagation: Carry bits propagate from the least significant nibble to the most significant nibble.
Sticky Saturation Flag: Detects if the final carry out is high (overflow). The flag remains set until cleared.
Synchronous Operation: Registered design with clock and active-low reset.
Control Interface: Includes start trigger, busy status, and clear_sat reset for the saturation flag.

Ports

Port Name	Direction	Width	Description
`clk`	Input	1	Clock input
`rst_n`	Input	1	Active-low reset
`clear_sat`	Input	1	Clear saturation flag
`a`	Input	16	First BCD operand
`b`	Input	16	Second BCD operand
`start`	Input	1	Start addition trigger
`busy`	Output	1	Unit is processing
`sum`	Output	16	Resulting BCD sum
`sticky_sat`	Output	1	Sticky saturation flag

Verification

The testbench covers:

Basic addition without carry propagation.
Carry propagation across multiple nibbles.
Saturation detection and sticky flag persistence.
Reset and clear saturation functionality.

All test cases passed in the simulation log.

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