Arithmetic & Math

8-Bit ALU Slice with Add/Sub and Logic Ops — L2 Upgrade

An 8-bit ALU slice supporting AND, OR, XOR, and unsigned addition with a sticky saturation flag for overflow detection.

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About this block

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8-Bit ALU Slice with Add/Sub and Logic Ops — L2 Upgrade is a Verilog reference block in the Arithmetic & Math catalog. Adders, multipliers, dividers, ALUs, and arithmetic datapaths. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This OpenIP provides an 8-bit Arithmetic Logic Unit (ALU) slice. It supports bitwise logic operations (AND, OR, XOR) and unsigned addition. A key feature is the sticky saturation flag (sat), which persists until explicitly cleared, allowing downstream logic to detect arithmetic overflows.

This IP implements a simple, educational 8-bit ALU with the following characteristics:

Operations: Bitwise AND, OR, XOR, and Unsigned Addition.
Overflow Handling: Detects unsigned addition overflow.
Sticky Flag: The sat output remains high after an overflow event until cleared by clr_sat or rst_n.
Zero Flag: Indicates when the result is zero.
Reset: Asynchronous active-low reset (rst_n).

This module is suitable for educational purposes, simple control logic, or as a building block in larger arithmetic units where overflow tracking is required.

Choose Open in IDE. RTL Studio loads the packaged workspace for 8-Bit ALU Slice with Add/Sub and Logic Ops — L2 Upgrade.
Read the Verilog module in the editor. The catalog line for this block: An 8-bit ALU slice supporting AND, OR, XOR, and unsigned addition with a sticky saturation flag for overflow detection.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

8-bit data path width for operands and results.
Four operation codes selected by a 2-bit control signal (op).
Bitwise Logic: AND, OR, XOR.
Unsigned Addition: With carry-out detection.
Sticky Saturation Flag (sat):

- Set to 1 when an addition overflow occurs. - Remains 1 (sticky) for subsequent logic operations or non-overflow additions. - Cleared synchronously by clr_sat or asynchronously by rst_n.

Zero Flag (zero): High if the 8-bit result is zero.
Asynchronous Active-Low Reset (rst_n).
Synchronous Clear for the saturation flag (clr_sat).

Ports

Port Name	Direction	Width	Description
`clk`	Input	1	Clock input
`rst_n`	Input	1	Asynchronous active-low reset
`clr_sat`	Input	1	Synchronous clear for saturation flag
`op`	Input	2	Operation select: `00`=AND, `01`=OR, `10`=XOR, `11`=ADD
`a`	Input	8	First operand
`b`	Input	8	Second operand
`result`	Output	8	ALU result
`zero`	Output	1	High if `result` is zero
`sat`	Output	1	Sticky saturation/overflow flag

Architecture

The module consists of two main parts:

Combinational ALU Core: Computes the result, zero flag, and raw overflow status based on the op signal.
Sequential Saturation Latch: A flip-flop that latches the overflow status, making it "sticky" until cleared.

### Logic Details

Logic Operations (00, 01, 10): The ALU performs bitwise operations. The raw overflow signal is forced to 0.
Addition (11): The ALU computes a 9-bit sum ({1'b0, a} + {1'b0, b}). The MSB (sum[8]) indicates unsigned overflow. This value drives the saturation latch.
Saturation Flag Behavior:

- On the positive clock edge, if overflow is high, sat becomes 1. - If clr_sat is high, sat is cleared to 0. - If rst_n is low, sat is cleared to 0. - Otherwise, sat retains its previous value (sticky).

Verification

The testbench (tb_alu.v) verifies all operations and the sticky saturation behavior using Icarus Verilog.

### Test Cases

Test Case	Description	Expected Result
TC1	AND operation	`result` = `a & b`, `sat` = 0
TC2	OR operation	`result` = `a	b`,` sat` = 0
TC3	XOR operation	`result` = `a ^ b`, `sat` = 0
TC4	ADD no overflow	`result` = `a + b`, `sat` = 0
TC5	ADD overflow	`result` = `a + b` (truncated), `sat` = 1
TC6	Clear saturation	`sat` = 0
TC7	Set saturation again	`sat` = 1
TC8	Sticky saturation	`sat` remains 1 after logic op
TC9	Final clear	`sat` = 0

### Running Simulation

To run the simulation:

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