Arithmetic & Math

32-Bit Count Leading Zeros

Combinational module that counts the number of leading zeros in a 32-bit input vector using a priority encoder approach.

Open in IDE Category Wiki · arithmetic

About this block

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32-Bit Count Leading Zeros is a Verilog reference block in the Arithmetic & Math catalog. Adders, multipliers, dividers, ALUs, and arithmetic datapaths. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This IP core counts the number of leading zeros in a 32-bit input vector. It implements a priority encoder approach for efficient combinational logic.

This IP provides a robust and simple solution for leading zero counting. It is suitable for use in normalization, floating-point arithmetic, and priority arbitration. The design is fully combinational and requires no clock or reset signals.

Choose Open in IDE. RTL Studio loads the packaged workspace for 32-Bit Count Leading Zeros.
Read the Verilog module in the editor. The catalog line for this block: Combinational module that counts the number of leading zeros in a 32-bit input vector using a priority encoder approach.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

Combinational Logic: No clock or reset required.
Priority Encoder: Efficient cascading if-else structure.
Edge Case Handling: Explicitly handles all-zero input (output 32).
Verified: All critical edge cases and random patterns validated via Icarus Verilog.

Ports

Port Name	Direction	Width	Description
`data_in`	Input	32	32-bit input data vector
`clz_out`	Output	5	Count of leading zeros (0-32)

Architecture

The module uses a cascading if-else structure to determine the first set bit. This approach ensures deterministic combinational delay. The logic checks bits from MSB (31) down to LSB (0). A special case handles the all-zero input condition.

Verification

The testbench validates all critical edge cases and random patterns. It checks for zero input, single bit set, and all bits set scenarios. Simulation uses Icarus Verilog for functional verification.

### Test Cases

Test Case	Input Hex	Expected Output	Result
TC1	0x00000000	32	PASS
TC2	0x00000001	31	PASS
TC3	0x80000000	0	PASS
TC4	0xFFFFFFFF	0	PASS
TC5	0x40000000	1	PASS
TC6	0x00000002	30	PASS
TC7	0x00000004	29	PASS

### Expected Simulation Output

After Run Simulation, the Log panel should show:

TC1 PASS - Input 0 yields 32
TC2 PASS - Input 1 yields 31
TC3 PASS - Input MSB set yields 0
TC4 PASS - Input All Ones yields 0
TC5 PASS - Input Bit 30 set yields 1
TC6 PASS - Input Bit 1 set yields 30
TC7 PASS - Input Bit 2 set yields 29
Simulation ends with INFO: PASS.

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