Arithmetic & Math

32-Bit Population Count — L1 Upgrade — L2 Upgrade

Registered 32-bit population counter with sticky saturation flag and clear capability.

Open in IDE Category Wiki · arithmetic

About this block

Simulate it in the Verilog IDE

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32-Bit Population Count — L1 Upgrade — L2 Upgrade is a Verilog reference block in the Arithmetic & Math catalog. Adders, multipliers, dividers, ALUs, and arithmetic datapaths. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This Intellectual Property (IP) implements a registered 32-bit population count (bit count) unit with a sticky saturation flag. It is designed for high-performance applications such as L1/L2 cache line monitoring, where tracking the density of set bits is critical.

### Key Features

Input Width: 32-bit data vector.
Output Width: 6-bit population count (0–32).
Sticky Saturation Flag: Asserts when the count reaches 32 (all bits set) and remains asserted until cleared.
Registered Output: Output updates on the positive clock edge when enabled.
Control Signals: Asynchronous active-low reset (rst_n) and synchronous clear for the saturation flag (clr).

### Typical Use Cases

Cache line occupancy monitoring.
Bit density analysis in data streams.
Error detection logic requiring bit count thresholds.

Choose Open in IDE. RTL Studio loads the packaged workspace for 32-Bit Population Count — L1 Upgrade — L2 Upgrade.
Read the Verilog module in the editor. The catalog line for this block: Registered 32-bit population counter with sticky saturation flag and clear capability.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Ports

Port Name	Direction	Width	Description
`clk`	Input	1	Clock input
`rst_n`	Input	1	Active-low asynchronous reset
`en`	Input	1	Enable signal for updating output
`data_in`	Input	32	Input data vector
`clr`	Input	1	Clear signal for saturation flag
`popcount_out`	Output	6	Registered population count
`sat_flag`	Output	1	Sticky saturation flag

Integration

To integrate this IP into your design:

Include the RTL file: rtl/popcount_registered_32_sticky_sat_flag.v
Instantiate the module as shown below:

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