Arithmetic & Math

8-Bit Count Trailing Zeros — L1 Upgrade — L2 Upgrade

Registered 8-bit Count Trailing Zeros unit with valid handshake and sticky saturation flag.

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8-Bit Count Trailing Zeros — L1 Upgrade — L2 Upgrade is a Verilog reference block in the Arithmetic & Math catalog. Adders, multipliers, dividers, ALUs, and arithmetic datapaths. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This IP core implements a registered 8-bit Count Trailing Zeros (CTZ) unit. It calculates the number of consecutive zero bits starting from the least significant bit (LSB) of an 8-bit input.

The module features a synchronous pipeline stage, a valid handshake interface for data control, and a sticky saturation flag that indicates when the input data is zero.

The saturation flag can be manually cleared via an input signal or automatically cleared when non-zero data is processed.

Choose Open in IDE. RTL Studio loads the packaged workspace for 8-Bit Count Trailing Zeros — L1 Upgrade — L2 Upgrade.
Read the Verilog module in the editor. The catalog line for this block: Registered 8-bit Count Trailing Zeros unit with valid handshake and sticky saturation flag.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

Input Width: 8 bits.
Output Width: 4 bits (covers range 0-8).
Pipeline: Single registered stage.
Reset: Active-low synchronous reset (rst_n).
Saturation Flag: Sticky behavior; set when input is 0, cleared when input is non-zero or via clear_sat.
Interface: Valid/Ready handshake (Valid only in this implementation).

Ports

Port Name	Direction	Width	Description
`clk`	Input	1	Clock input
`rst_n`	Input	1	Active-low synchronous reset
`valid_i`	Input	1	Valid input signal; data is processed when high
`data_i`	Input	[7:0]	8-bit input data
`clear_sat`	Input	1	Clear saturation flag (active high)
`valid_o`	Output	1	Valid output signal; high when data is valid
`ctz_o`	Output	[3:0]	Count Trailing Zeros result
`sat_o`	Output	1	Saturation flag; high if input was zero

Architecture

The module operates as a registered pipeline stage. On the rising edge of clk, if valid_i is high, the input data_i is sampled. The CTZ logic determines the index of the first set bit (LSB to MSB).

If data_i is zero, ctz_o is set to 8, and sat_o is set to 1.
If data_i is non-zero, ctz_o is set to the index of the first set bit, and sat_o is cleared to 0.
The valid_o signal is asserted high when valid_i is high, indicating that the output data is valid.
The sat_o flag is sticky. It remains high until clear_sat is asserted or until a non-zero input is processed.

Verification

The provided testbench verifies the following scenarios:

Basic CTZ Values: Tests inputs that are powers of two (0x01, 0x02, 0x04, etc.).
Saturation Flag: Tests input 0x00 to verify saturation flag is set.
Clear Saturation: Tests manual clearing of the saturation flag.
Sticky Behavior: Verifies that the saturation flag remains set until cleared or overwritten by non-zero data.
Edge Cases: Tests 0xFF (ctz=0) and 0x80 (ctz=7).
Reset: Verifies that all outputs are cleared on reset.

### Test Results

Test Case	Description	Expected Result	Status
TC1a	data=0x01	ctz=0, valid=1	PASS
TC1b	data=0x02	ctz=1, valid=1	PASS
TC1c	data=0x04	ctz=2, valid=1	PASS
TC1d	data=0x08	ctz=3, valid=1	PASS
TC1e	data=0x10	ctz=4, valid=1	PASS
TC1f	data=0x80	ctz=7, valid=1	PASS
TC2a	data=0x00	sat=1, ctz=8, valid=1	PASS
TC2b	clear_sat	sat=0	PASS
TC2c	data=0x00 again	sat=1	PASS
TC3	data=0x01	sat=0, ctz=0	PASS
TC4a	data=0xFF	ctz=0, valid=1	PASS
TC4b	data=0x80	ctz=7, valid=1	PASS

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