Arithmetic & Math

8-Bit EQ/GT/LT Comparator — L1 Upgrade — L2 Upgrade

8-bit registered comparator with equality, greater-than, less-than outputs and a sticky saturation flag.

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About this block

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8-Bit EQ/GT/LT Comparator — L1 Upgrade — L2 Upgrade is a Verilog reference block in the Arithmetic & Math catalog. Adders, multipliers, dividers, ALUs, and arithmetic datapaths. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This IP core implements an 8-bit registered comparator capable of determining equality, greater-than, and less-than relationships between two unsigned operands (a and b).

It features registered outputs for stable timing and a sticky saturation flag that indicates when the absolute difference between inputs exceeds 127 (0x7F).

The saturation flag persists until explicitly cleared via the clear_sat signal.

Choose Open in IDE. RTL Studio loads the packaged workspace for 8-Bit EQ/GT/LT Comparator — L1 Upgrade — L2 Upgrade.
Read the Verilog module in the editor. The catalog line for this block: 8-bit registered comparator with equality, greater-than, less-than outputs and a sticky saturation flag.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Architecture

Clock Domain: Single clock domain (clk).
Reset: Active-low asynchronous reset (rst_n).
Inputs: Two 8-bit unsigned operands (a, b).
Logic:

- Combinational comparison logic calculates relationships. - Sequential logic registers outputs on posedge clk. - Saturation logic checks if the difference exceeds the threshold of 127.

Ports

Port Name	Direction	Width	Description
clk	Input	1	Clock input
rst_n	Input	1	Active-low asynchronous reset
clear_sat	Input	1	Active-high clear for saturation flag
a	Input	8	Input operand A
b	Input	8	Input operand B
eq	Output	1	Asserted when a equals b
gt	Output	1	Asserted when a is greater than b
lt	Output	1	Asserted when a is less than b
sat_flag	Output	1	Sticky saturation flag

Verification

The design has been verified using a testbench that covers:

Reset behavior
Equality, Greater-Than, and Less-Than comparisons
Saturation detection for large differences (both a > b and b > a)
Sticky behavior of the saturation flag
Clear functionality of the saturation flag

### Test Results

All 12 test cases passed successfully:

TC1: Reset behavior
TC2-TC4: Basic comparisons (EQ, GT, LT)
TC5-TC6: Saturation detection (large differences)
TC7-TC11: Saturation flag sticky and clear behavior
TC12: Zero difference edge case

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