Arithmetic & Math

Kogge-Stone Parallel Prefix Adder

Parameterized combinational Kogge-Stone adder with carry-in, carry-out, and signed overflow detection.

Open in IDE Category Wiki · arithmetic

About this block

Simulate it in the Verilog IDE

Mediumsystemverilogsimsyn

Kogge-Stone Parallel Prefix Adder is a SystemVerilog reference block in the Arithmetic & Math catalog. Adders, multipliers, dividers, ALUs, and arithmetic datapaths. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

Parameterized combinational adder built with a Kogge-Stone parallel prefix tree. It computes sum = a + b + cin in a single logic depth of O(log WIDTH) carry stages and exposes unsigned carry-out plus optional signed overflow detection.

The default width is 32 bits. The testbench also instantiates 8-bit and 16-bit variants to confirm parameterization.

clk, rst_n, and ce are present for system integration but are not used inside the combinational core.

Choose Open in IDE. RTL Studio loads the packaged workspace for Kogge-Stone Parallel Prefix Adder.
Read the SystemVerilog module in the editor. The catalog line for this block: Parameterized combinational Kogge-Stone adder with carry-in, carry-out, and signed overflow detection.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Ports

Name	Direction	Type	Width	Description
`signed_mode`	input	logic	1	1 = assert `overflow` on signed wrap
`ce`	input	logic	1	Unused (integration placeholder)
`a`	input	logic	WIDTH	Augend
`b`	input	logic	WIDTH	Addend
`cin`	input	logic	1	Carry in
`sum`	output	logic	WIDTH	Sum result
`cout`	output	logic	1	Unsigned carry out
`overflow`	output	logic	1	Signed overflow (MSB carry mismatch)

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