Arithmetic & Math
Parameterized Ripple-Carry Adder
A fully parameterized Verilog ripple-carry adder with carry-in, carry-out, and signed overflow detection.
About this block
Simulate it in the Verilog IDE
Parameterized Ripple-Carry Adder is a Verilog reference block in the Arithmetic & Math catalog. Adders, multipliers, dividers, ALUs, and arithmetic datapaths. Marked Easy: a small block you can read, simulate, and synthesize in one sitting.
This IP implements a fully parameterized ripple-carry adder in Verilog. It supports arbitrary bit-widths via the WIDTH parameter. The design includes carry-in (cin), carry-out (cout), and signed overflow (ovf) flags. It is suitable for low-complexity arithmetic or educational purposes.
This parameterized ripple-carry adder provides a simple, synthesizable solution for fixed-width addition. It correctly handles unsigned carry-out and signed overflow detection for two's complement numbers. The design is verified against comprehensive test cases including edge conditions and random inputs. Integrators should consider the linear delay for high-performance applications and opt for faster adder architectures if necessary.
- Choose Open in IDE. RTL Studio loads the packaged workspace for Parameterized Ripple-Carry Adder.
- Read the Verilog module in the editor. The catalog line for this block: A fully parameterized Verilog ripple-carry adder with carry-in, carry-out, and signed overflow detection.
- Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
- Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.
RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.
Architecture
The adder uses a generate-for loop to instantiate full-adder logic for each bit slice. Carry signals propagate sequentially from the least significant bit to the most significant bit. This creates a linear delay path proportional to the word width.
Interface
| Port Name | Direction | Width | Description |
|---|---|---|---|
a | Input | WIDTH-1:0 | First operand |
b | Input | WIDTH-1:0 | Second operand |
cin | Input | 1 | Carry-in bit |
sum | Output | WIDTH-1:0 | Sum result |
cout | Output | 1 | Carry-out bit |
ovf | Output | 1 | Signed overflow flag |
Parameters
| Parameter | Default | Description |
|---|---|---|
WIDTH | 8 | Bit-width of operands and sum |
Verification
The testbench covers basic addition, maximum value handling, and signed overflow conditions. It also includes randomized test cases to verify correctness across various input combinations. All tests passed successfully using the Icarus Verilog simulator.
| Test Case | Description | Result |
|---|---|---|
| TC1 | Basic 0 + 0 | PASS |
| TC2 | Basic 1 + 1 | PASS |
| TC3 | Max + 1 (Unsigned Overflow) | PASS |
| TC4 | Signed Overflow (Pos + Pos) | PASS |
| TC5 | Signed Overflow (Neg + Neg) | PASS |
| TC6 | Carry-in = 1 | PASS |
| TC7 | Random Mixed Cases | PASS |
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