Arithmetic & Math

BCD Subtractor 4-Digit — L2 Upgrade

A 4-digit Binary Coded Decimal subtractor with sticky saturation flag and underflow detection.

Open in IDE Category Wiki · arithmetic

About this block

Simulate it in the Verilog IDE

Mediumverilogsimsyn

BCD Subtractor 4-Digit — L2 Upgrade is a Verilog reference block in the Arithmetic & Math catalog. Adders, multipliers, dividers, ALUs, and arithmetic datapaths. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This IP core implements a 4-digit Binary Coded Decimal (BCD) subtractor designed for educational Level 2 difficulty.

It performs saturated arithmetic, ensuring that if the minuend is less than the subtrahend, the result is clamped to zero and a sticky saturation flag is asserted.

The module processes four independent 4-bit BCD digits, handling borrows correctly between positions.

Choose Open in IDE. RTL Studio loads the packaged workspace for BCD Subtractor 4-Digit — L2 Upgrade.
Read the Verilog module in the editor. The catalog line for this block: A 4-digit Binary Coded Decimal subtractor with sticky saturation flag and underflow detection.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

4-Digit BCD Support: Handles values from 0000 to 9999.
Saturated Arithmetic: Results clamp to 0 on underflow.
Sticky Saturation Flag: sat_flag remains high until manually cleared.
Synchronous Output: Outputs registered on the positive clock edge.
Asynchronous Reset: Active-low reset initializes all states to zero.

Architecture

The design utilizes a combinatorial subtraction core with synchronous output registration. On every positive clock edge, the outputs (diff and sat_flag) are updated based on the current inputs and internal state. An active-low asynchronous reset (rst_n) initializes all internal states to zero. The saturation logic detects global underflow (minuend < subtrahend) and sets the sticky flag. The sticky behavior ensures the flag remains asserted even after the subtraction operation completes, aiding in debugging and error handling.

### Block Diagram

Ports

Port Name	Direction	Width	Description
`clk`	Input	1	Clock input for synchronous logic.
`rst_n`	Input	1	Active-low asynchronous reset.
`clear_sat`	Input	1	Clears the sticky saturation flag.
`sub_en`	Input	1	Enable signal to trigger subtraction.
`minuend`	Input	16	4-digit BCD minuend value (0000-9999).
`subtrahend`	Input	16	4-digit BCD subtrahend value (0000-9999).
`diff`	Output	16	Resulting 4-digit BCD difference.
`sat_flag`	Output	1	Sticky saturation indicator (1 if underflow occurred).

Verification

The testbench validates basic subtraction operations, underflow detection, sticky saturation behavior, and the clear functionality. It ensures that outputs hold their previous values when sub_en is deasserted.

### Test Cases

Test Case	Description	Expected Result
TC1	Basic Subtraction	`diff` is `1233`, `sat_flag` is `0`.
TC2	Underflow	`sat_flag` is `1`.
TC3	Sticky Saturation	`sat_flag` remains `1` after clear cycle if underflow occurred.
TC4	Clear Saturation	`sat_flag` is `0` after `clear_sat` pulse.
TC5	Hold State	`diff` holds previous value when `sub_en` is `0`.

### Simulation Log

Upon successful verification, the simulation log should display:

Constraints

Max Frequency: Depends on target FPGA/ASIC technology. Typical LUT-based FPGAs can support >100 MHz.
Input Validity: Inputs minuend and subtrahend must be valid BCD (0-9 per nibble). Behavior is undefined for invalid BCD codes (10-15).

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