Arithmetic & Math

Carry-Lookahead Adder 4-Bit — L2 Upgrade

4-bit unsigned carry-lookahead adder with immediate saturation flag and sticky latched saturation flag for overflow monitoring.

Open in IDE Category Wiki · arithmetic

About this block

Simulate it in the Verilog IDE

Mediumverilogsimsyn

Carry-Lookahead Adder 4-Bit — L2 Upgrade is a Verilog reference block in the Arithmetic & Math catalog. Adders, multipliers, dividers, ALUs, and arithmetic datapaths. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This IP core implements a high-performance 4-bit unsigned carry-lookahead adder (CLA) with integrated saturation detection. Unlike standard ripple-carry adders, this design utilizes parallel generate/propagate logic to achieve constant-time addition latency, making it suitable for high-speed fixed-point arithmetic pipelines.

### Key Features

Constant Latency: Carry-lookahead architecture ensures addition time is independent of operand magnitude.
Saturation Monitoring: Provides immediate overflow detection via sat_flag.
Sticky Latch: A synchronous sticky flag (sticky_sat) latches overflow events until explicitly cleared, facilitating robust error handling in system-level designs.
Standard Interface: Simple synchronous interface with active-low reset.

Constant Latency: Carry-lookahead architecture ensures addition time is independent of operand magnitude.
Saturation Monitoring: Provides immediate overflow detection via sat_flag.
Sticky Latch: A synchronous sticky flag (sticky_sat) latches overflow events until explicitly cleared, facilitating robust error handling in system-level designs.
Standard Interface: Simple synchronous interface with active-low reset.

Choose Open in IDE. RTL Studio loads the packaged workspace for Carry-Lookahead Adder 4-Bit — L2 Upgrade.
Read the Verilog module in the editor. The catalog line for this block: 4-bit unsigned carry-lookahead adder with immediate saturation flag and sticky latched saturation flag for overflow monitoring.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Architecture

The core consists of three main stages:

Generate/Propagate Logic: Computes g[i] = a[i] & b[i] and p[i] = a[i] | b[i] for all bit slices in parallel.
Carry Lookahead Unit: Resolves the carry chain using the formula c[i+1] = g[i] | (p[i] & c[i]). This parallel resolution minimizes propagation delay compared to ripple-carry.
Sum and Flag Logic: Computes the final sum bits via XOR and drives the saturation flags.

Ports

Port Name	Direction	Width	Description
`clk`	Input	1	Clock input for synchronous sticky latch
`rst_n`	Input	1	Active-low asynchronous reset
`clr_sticky`	Input	1	Synchronous clear for sticky_sat flag
`a`	Input	4	First 4-bit unsigned operand
`b`	Input	4	Second 4-bit unsigned operand
`sum`	Output	4	4-bit sum result (wraps on overflow)
`sat_flag`	Output	1	High if unsigned overflow occurs (c_out)
`sticky_sat`	Output	1	Latched saturation flag, cleared by `clr_sticky`

Verification

The provided testbench (tb_carry_lookahead_adder_4bit_sticky_sat_flag.v) validates:

Normal addition without overflow.
Saturation detection at the 4-bit boundary (e.g., 8 + 8).
Latching behavior of the sticky flag.
Synchronous clearing of the sticky flag.
Behavior with maximum unsigned values (15 + 1).

Run the simulation using Icarus Verilog or your preferred simulator to verify functionality.

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