Arithmetic & Math

Clamp Signed 8-bit — L1 Upgrade — L2 Upgrade

Registered signed 8-bit clamp with sticky saturation flag and explicit clear.

Open in IDE Category Wiki · arithmetic

About this block

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Clamp Signed 8-bit — L1 Upgrade — L2 Upgrade is a Verilog reference block in the Arithmetic & Math catalog. Adders, multipliers, dividers, ALUs, and arithmetic datapaths. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This IP implements a registered signed 8-bit clamp with sticky saturation flag. It passes input data through when within the valid signed 8-bit range. It detects saturation at the exact boundaries of -128 and 127. The saturation flag is sticky until explicitly cleared by the clear_sat signal. The output is registered on the positive clock edge when enabled.

This module provides a simple registered clamp with sticky saturation detection for signed 8-bit data. It is suitable for applications requiring boundary monitoring with explicit flag management.

Choose Open in IDE. RTL Studio loads the packaged workspace for Clamp Signed 8-bit — L1 Upgrade — L2 Upgrade.
Read the Verilog module in the editor. The catalog line for this block: Registered signed 8-bit clamp with sticky saturation flag and explicit clear.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

Registered 8-bit signed data path.
Sticky saturation flag for boundary conditions.
Asynchronous active-low reset.
Enable control for data holding.
Explicit clear for the saturation flag.

Ports

Port Name	Direction	Width	Description
`clk`	Input	1	Clock input
`rst_n`	Input	1	Active-low asynchronous reset
`en`	Input	1	Enable input
`data_in`	Input	8	Signed 8-bit data input
`clear_sat`	Input	1	Clear saturation flag input
`data_out`	Output	8	Registered signed 8-bit data output
`sat_flag`	Output	1	Sticky saturation flag output

Verification

The testbench covers reset behavior, normal clamping, saturation detection, and flag control. All eight test cases passed successfully in the simulation log.

Test Case	Description	Result
TC1	Reset Test	PASS
TC2	Normal Clamping Positive	PASS
TC3	Normal Clamping Negative	PASS
TC4	Saturation Upper Bound	PASS
TC5	Saturation Lower Bound	PASS
TC6	Sticky Flag Clear	PASS
TC7	Enable Control	PASS
TC8	Re-enable and New Value	PASS

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